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VHDL - Add Delay to Flip-Flop

  1. Apr 13, 2008 #1
    Hi, I have a small piece of code that will detect a rising edge and output a pulse for 2 clock cycles. I'm only doing this for simulation purposes and will not be porting this into a FPGA.

    When using the after 10 ns after a statement, I know this is ignored during sythesis. How can I implement a delay and have it be shown on the testbench waveform?

    Thanks. I'm using Xilinx's ISE WebPACK Software. Code is below.

    Code (Text):
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity rising_edge_detector_2ms is
        Port (
                  clk : in  STD_LOGIC;
               signal_input : in  STD_LOGIC;
                  out1, out2 : out STD_LOGIC;
               output : out  STD_LOGIC
                 );  
    end rising_edge_detector_2ms;


    architecture Behavioral of rising_edge_detector_2ms is

    signal Q_FF, Q1_FF, Q2_FF : STD_LOGIC;

    begin

        process(clk)
        begin
            if rising_edge(clk) then
                Q_FF <= signal_input after 20 ns;
            end if;
        end process;
       
        process(clk)
        begin
            if rising_edge(clk) then
                Q1_FF <= Q_FF  after 20 ns;
            end if;
        end process;
       
        process(clk)
        begin
            if rising_edge(clk) then
                Q2_FF <= Q1_FF  after 20 ns;
            end if;
        end process;
       
    -- Final Output Through AND Gate
        out1 <= Q1_FF;
        out2 <= Q2_FF;
        output <= (not Q2_FF) and signal_input;

    end Behavioral;

     
     
  2. jcsd
  3. Apr 15, 2008 #2
    I've had to create a purely VHDL one-shot type of behavior..which is pretty annoying.

    Code (Text):

    --5 second one shot
    Process (onehertz, fivetrigger, reset)
        variable fiveint: integer range 0 to 4;
    begin
        if (reset = '0') then
            fivesec <= '1';
            fiveint := 0;
        elsif (rising_edge(onehertz)) then
            if (fivetrigger = '0') then
                fiveint := 0;
                fivesec <= '1';
            elsif (fiveint = 4) then
                fivesec <= '0';
            else
                fiveint := fiveint + 1;
            end if;
        end if;
    end process;
     
    Not truly a one-shot since the trigger has to stay on the whole time, but if you create a state machine where a certain state enables this trigger, you can do it.

    My thought process was:

    State 1 goes to State 2 when the input goes high
    State 2 enables this counting process
    State 2 goes back to State 1 when counting is done.

    It's bootleg but I got an A so it's all good.
     
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