VHDL code for binary counter

[tetooo_2006]

Homework Statement

structure or behavior VHDL code of a 5-bits binary counter with a sync. load signal to preset the counter to a specific initial state. the output of the counter (Q0 to Q4) are connected to a binary decoder that shows the state of the counter.

Homework Equations

The Attempt at a Solution

I wrote the code of 5 bits counter

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY counter IS
PORT ( count : OUT unsigned (4 DOWNTO 0);
load : IN STD_LOGIC;
pre :IN unsigned (4 DOWNTO 0);
Clk : IN STD_LOGIC);
END counter;
ARCHITECTURE Behavioral OF counter IS
SIGNAL c : unsigned(4 DOWNTO 0) := "00000";

BEGIN
count <= c;
PROCESS(Clk)
BEGIN
IF( rising_edge(Clk) ) THEN
IF(load = '1') THEN
c <= pre;
ELSE
c <= c + 1;
END IF;
END IF;
END PROCESS;
END Behavioral;

I want to connect the output to a binary decoder that shows the state of the counter
how can i do that?

 

[DaveE]

You can just define the decoder outputs and then assign each bit of c to an output. It doesn't have to be a process. Alternatively, you can just define c as an output (array) instead of a signal.