How to Correct VHDL Code for Serial Input State Machine?

[ellis91]

VHDL help in state machines!

I have to write a vhdl code to accept inputs serially in the form of bytes(1 byte at a time). These bytes are in a particular order i.e they are received in packets where each packet is a frame with a specific number of bytes. This number of bytes in a frame can be defined by the user and is fixed. The main purpose of my code is to:
1. Assign one special byte to mark the beginning of each frame.
2. Search for the special byte in order to start receving data.
3. If the special byte is not found at regular intervals i.e after the number of bytes that the user defined, an error is indicated. Variables to keep count of the errors and the number of special bytes are assigned.
4. If the special byte is found before or after the specific number of bytes, then besides indicating an error, the code should resume receiving data from that special byte.

I know that i have to go about it using state machines, but i don't exactly understnd how the structure of the program and states should be

This was my attempt at the program and i know it is wrong. how can i correct it to do what i want it to do:

-- [B][COLOR="Blue"][B][B]entity packet_format_error_detection is
port (

      data_receive, special_byte : in STD_LOGIC_VECTOR(0 to 7);
        no_of_bytes : in STD_LOGIC_VECTOR(0 to 7);
        clock, subclock : in STD_LOGIC
       
        );
           
end final_packet_format_error_detection;

architecture statemachine of packet_format_error_detection is
 
 type statetype is (IDLE, START_DETECTION, RECEIVE_DATA);
 signal state, next_state: statetype;
 signal no_error_bytes : integer range  0 to 1024;
 signal no_special_bytes : integer range 0 to 1024;
 signal byte_count : integer range 0 to 1024;
begin


operation: process(state, data_receive, special_byte, no_of_bytes, no_error_bytes, no_special_bytes )

begin
 
no_error_bytes <= 0;
no_special_bytes <= 0;
byte_count <= 0;

case state is

when IDLE => if(data_receive = special_byte) then
                 next_state <=    START_DETECTION;
                 else next_state <= IDLE;
                 end if;

when START_DETECTION => if( clock'event and clock = '1') then
                                    next_state <= RECEIVE_DATA;
                                else
                                    next_state <= START_DETECTION;
                                end if;
                               
when RECEIVE_DATA => if( subclock'event and subclock = '1') then
                                byte_count <= byte_count + 1;
                                 if(data_receive = special_byte) then
                                    if(byte_count = no_of_bytes) then
                                        no_special_bytes <= no_special_bytes + 1;
                                        byte_count <= 0;
                                        next_state <= IDLE;
                                    else
                                        no_special_bytes <= no_special_bytes + 1;
                                        no_error_bytes <= no_error_bytes + 1;
                                        byte_count <= 0;
                                        next_state <= RECEIVE_DATA;
                                    end if;
                                 else
                                    next_state <= RECEIVE_DATA;
                                 end if;
                            else
                                    next_state <= RECEIVE_DATA;
                            end if;
end case;
                end process;
end statemachine;
[/B][/B][/COLOR][/B]

I can explain it in even better detail if necessary. Please help me at the earliest.

 

[KingNothing]

Can you provide some documentation on the design you are using? Graphs, flowcharts, processes, etc.

It is very difficult to "correct" code when you don't know the design information.

 

[ellis91]

the main reason i put up the code was to give you an idea as to how i was approachin it.. i want help in finding out if this approach is good or there are other better ways of achieving the result.. i would like to know how to frame the logic of this program.. thanks in advance..

 

[berkeman]

I have to write a vhdl code to accept inputs serially in the form of bytes(1 byte at a time). These bytes are in a particular order i.e they are received in packets where each packet is a frame with a specific number of bytes. This number of bytes in a frame can be defined by the user and is fixed. The main purpose of my code is to:
1. Assign one special byte to mark the beginning of each frame.
2. Search for the special byte in order to start receving data.
3. If the special byte is not found at regular intervals i.e after the number of bytes that the user defined, an error is indicated. Variables to keep count of the errors and the number of special bytes are assigned.
4. If the special byte is found before or after the specific number of bytes, then besides indicating an error, the code should resume receiving data from that special byte.

I know that i have to go about it using state machines, but i don't exactly understnd how the structure of the program and states should be

This was my attempt at the program and i know it is wrong. how can i correct it to do what i want it to do:

-- [B][COLOR="Blue"][B][B]entity packet_format_error_detection is
port (

      data_receive, special_byte : in STD_LOGIC_VECTOR(0 to 7);
        no_of_bytes : in STD_LOGIC_VECTOR(0 to 7);
        clock, subclock : in STD_LOGIC
       
        );
           
end final_packet_format_error_detection;

architecture statemachine of packet_format_error_detection is
 
 type statetype is (IDLE, START_DETECTION, RECEIVE_DATA);
 signal state, next_state: statetype;
 signal no_error_bytes : integer range  0 to 1024;
 signal no_special_bytes : integer range 0 to 1024;
 signal byte_count : integer range 0 to 1024;
begin


operation: process(state, data_receive, special_byte, no_of_bytes, no_error_bytes, no_special_bytes )

begin
 
no_error_bytes <= 0;
no_special_bytes <= 0;
byte_count <= 0;

case state is

when IDLE => if(data_receive = special_byte) then
                 next_state <=    START_DETECTION;
                 else next_state <= IDLE;
                 end if;

when START_DETECTION => if( clock'event and clock = '1') then
                                    next_state <= RECEIVE_DATA;
                                else
                                    next_state <= START_DETECTION;
                                end if;
                               
when RECEIVE_DATA => if( subclock'event and subclock = '1') then
                                byte_count <= byte_count + 1;
                                 if(data_receive = special_byte) then
                                    if(byte_count = no_of_bytes) then
                                        no_special_bytes <= no_special_bytes + 1;
                                        byte_count <= 0;
                                        next_state <= IDLE;
                                    else
                                        no_special_bytes <= no_special_bytes + 1;
                                        no_error_bytes <= no_error_bytes + 1;
                                        byte_count <= 0;
                                        next_state <= RECEIVE_DATA;
                                    end if;
                                 else
                                    next_state <= RECEIVE_DATA;
                                 end if;
                            else
                                    next_state <= RECEIVE_DATA;
                            end if;
end case;
                end process;
end statemachine;
[/B][/B][/COLOR][/B]

I can explain it in even better detail if necessary. Please help me at the earliest.

the main reason i put up the code was to give you an idea as to how i was approachin it.. i want help in finding out if this approach is good or there are other better ways of achieving the result.. i would like to know how to frame the logic of this program.. thanks in advance..

Welcome to the PF.

I agree with KingNothing -- please at least post your State Diagram to help make it easier to go through your code. Thanks.

 

[DeeNos]

I can understand your confusion and frustration with using VHDL in state machines. State machines can be a complex concept to grasp, but once you understand the structure and logic behind it, it becomes much easier to implement.

In your code, I notice that you have defined three states: IDLE, START_DETECTION, and RECEIVE_DATA. This is a good start, but it may be helpful to add a few more states to cover all possible scenarios. For example, you may want to add a state for when the special byte is not found at all, or when there are multiple special bytes in a frame. This will make your code more robust and handle all possible situations.

In addition, it may be helpful to define some variables to keep track of the current state, the number of bytes received, and the number of errors. This will make it easier to debug and troubleshoot your code.

Another important aspect to consider is the timing of your code. In state machines, timing is critical, and you need to make sure that your code is synchronized with the clock and subclock signals. This will ensure that your code is executing at the right time and in the correct sequence.

I would also recommend breaking down your code into smaller, more manageable processes. This will make it easier to understand and debug. For example, you can have one process to handle the special byte detection and another process to handle the receiving of data.

Overall, the key to successfully implementing VHDL in state machines is to have a clear understanding of the logic and structure behind it. Take your time to carefully plan and design your code, and don't be afraid to seek help or consult resources for guidance. With practice and patience, you will be able to create a robust and efficient state machine for your project.