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VHDL help

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  1. Mar 9, 2015 #1
    I'm super confused on why I keep getting an error on this code. I feel like I've tried everything but now I've run into mental block lol. My error message is:
    Error (10380): VHDL error at lab2.vhd(6): std_logic type is used but not declared as an array type

    Here is the code I came up with.
    Code (Text):

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    ENTITY lab2 IS
    PORT(
      A: IN BIT_VECTOR (3 downto 0);
      Y: OUT STD_LOGIC (9 downto 0));
    END lab2;
    ARCHITECTURE CIRCUIT OF lab2 IS
    BEGIN
    WITH A SELECT
       Y<= "1111110" WHEN "0000",
         "0110000" WHEN "0001",
        "1101101" WHEN "0010",
        "1111001" WHEN "0011",
        "0110011" WHEN "0100",
        "1011011" WHEN "0101",
        "1011111" WHEN "0110",
        "1110000" WHEN "0111",
        "1111111" WHEN "1000",
        "1110011" WHEN "1001";

    END CIRCUIT;

    Mind you, I started on VHDL last week so I know there is a lot I still need to grasp for this language.
     
    Last edited by a moderator: Mar 9, 2015
  2. jcsd
  3. Mar 9, 2015 #2

    berkeman

    User Avatar

    Staff: Mentor

    I inserted code tags for readability.

    When you search Help for std_logic, what comes up?
     
  4. Mar 10, 2015 #3
    Just looking at it,
    perhaps you should use
    Y: OUT std_logic_vector(9 downto 0));
     
  5. Mar 17, 2015 #4
    Hello Steve,

    std_logic is a signal or variable wich contains one bit.
    std_logic_vector is a sigal or variable wich contains an array
    you have to do the same for you Y (Y: OUT STD_LOGIC_VECTOR(9 downto 0)
     
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