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VHDL Register File Test Bench

  1. Feb 25, 2012 #1
    I am trying to implement a register file and a test bench in VHDL. I think I have the register file itself done ok so I just have to test it with the test bench now. I'm a little unsure as to how write the stimulus process however and was hoping that someone could point me the right way. This is what I have so far:

    Register File
    Code (Text):
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity register_file is
        Port ( src_s0 : in  STD_LOGIC;
               src_s1 : in  STD_LOGIC;
               des_A0 : in  STD_LOGIC;
               des_A1 : in  STD_LOGIC;
               Clk : in  STD_LOGIC;
               data_src : in  STD_LOGIC;
               data : in  STD_LOGIC_VECTOR (15 downto 0);
               reg0 : out  STD_LOGIC_VECTOR (15 downto 0);
               reg1 : out  STD_LOGIC_VECTOR (15 downto 0);
               reg2 : out  STD_LOGIC_VECTOR (15 downto 0);
               reg3 : out  STD_LOGIC_VECTOR (15 downto 0));
    end register_file;

    architecture Behavioral of register_file is
    -- components

        -- 16 bit Register for register file
        COMPONENT reg4
        PORT(
                D : IN std_logic_vector(15 downto 0);
                load : IN std_logic;
                Clk : IN std_logic;
                Q : OUT std_logic_vector(15 downto 0)
                );
        END COMPONENT;
       
        -- 2 to 4 Decoder
        COMPONENT decoder_2to4
        PORT(
                A0 : IN std_logic;
                A1 : IN std_logic;
                Q0 : OUT std_logic;
                Q1 : OUT std_logic;
                Q2 : OUT std_logic;
                Q3 : OUT std_logic
                );
        END COMPONENT;
       
        -- 2 to 1 line multiplexer
        COMPONENT mux2_4bit
        PORT(
                In0 : IN std_logic_vector(15 downto 0);
                In1 : IN std_logic_vector(15 downto 0);
                s : IN std_logic;
                Z : OUT std_logic_vector(15 downto 0)
                );
        END COMPONENT;
       
        -- 4 to 1 line multiplexer
        COMPONENT mux4_4bit
        PORT(
                In0 : IN std_logic_vector(15 downto 0);
                In1 : IN std_logic_vector(15 downto 0);
                In2 : IN std_logic_vector(15 downto 0);
                In3 : IN std_logic_vector(15 downto 0);
                S0 : IN std_logic;
                S1 : IN std_logic;
                Z : OUT std_logic_vector(15 downto 0)
                );
        END COMPONENT;


    -- signals
    signal load_reg0, load_reg1, load_reg2, load_reg3 : std_logic;
    signal reg0_q, reg1_q, reg2_q, reg3_q,
                data_src_mux_out, src_reg : std_logic_vector(15 downto 0);


    begin
    -- port maps

        --register 0
        reg00: reg4 PORT MAP(
                    D => data_src_mux_out,
                    load => load_reg0,
                    Clk => Clk,
                    Q => reg0_q
        );
       
        --register 1
        reg01: reg4 PORT MAP(
                    D => data_src_mux_out,
                    load => load_reg1,
                    Clk => Clk,
                    Q => reg1_q
        );
       
        --register 2
        reg02: reg4 PORT MAP(
                    D => data_src_mux_out,
                    load => load_reg2,
                    Clk => Clk,
                    Q => reg2_q
        );
       
        --register 3
        reg03: reg4 PORT MAP(
                    D => data_src_mux_out,
                    load => load_reg3,
                    Clk => Clk,
                    Q => reg3_q
        );
       
        -- Destination register decoder
        des_decoder_2to4: decoder_2to4 PORT MAP(
                    A0 => des_A0,
                    A1 => des_A1,
                    Q0 => load_reg0,
                    Q1 => load_reg1,
                    Q2 => load_reg2,
                    Q3 => load_reg3
        );
       
        -- 2 to 1 Data source multiplexer
        data_src_mux2_4bit: mux2_4bit PORT MAP(
                    In0 => data,
                    In1 => src_reg,
                    s => data_src,
                    Z => data_src_mux_out
        );
       
        -- 4to 1 source register multiplexer
        Inst_mux4_4bit: mux4_4bit PORT MAP(
                    In0 => reg0_q,
                    In1 => reg1_q,
                    In2 => reg2_q,
                    In3 => reg3_q,
                    S0 => src_s0,
                    S1 => src_s1,
                    Z => src_reg
        );
       
        reg0 <= reg0_q;
        reg1 <= reg1_q;
        reg2 <= reg2_q;
        reg3 <= reg3_q;
       
    end Behavioral;
     
    Register File test bench
    Code (Text):
    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
     
    -- Uncomment the following library declaration if using
    -- arithmetic functions with Signed or Unsigned values
    --USE ieee.numeric_std.ALL;
     
    ENTITY register_file_tb IS
    END register_file_tb;
     
    ARCHITECTURE behavior OF register_file_tb IS
     
        -- Component Declaration for the Unit Under Test (UUT)
     
        COMPONENT register_file
        PORT(
             src_s0 : IN  std_logic;
             src_s1 : IN  std_logic;
             des_A0 : IN  std_logic;
             des_A1 : IN  std_logic;
             Clk : IN  std_logic;
             data_src : IN  std_logic;
             data : IN  std_logic_vector(15 downto 0);
             reg0 : OUT  std_logic_vector(15 downto 0);
             reg1 : OUT  std_logic_vector(15 downto 0);
             reg2 : OUT  std_logic_vector(15 downto 0);
             reg3 : OUT  std_logic_vector(15 downto 0)
            );
        END COMPONENT;
       

       --Inputs
       signal src_s0 : std_logic := '0';
       signal src_s1 : std_logic := '0';
       signal des_A0 : std_logic := '0';
       signal des_A1 : std_logic := '0';
       signal Clk : std_logic := '0';
       signal data_src : std_logic := '0';
       signal data : std_logic_vector(15 downto 0) := (others => '0');

        --Outputs
       signal reg0 : std_logic_vector(15 downto 0);
       signal reg1 : std_logic_vector(15 downto 0);
       signal reg2 : std_logic_vector(15 downto 0);
       signal reg3 : std_logic_vector(15 downto 0);

       -- Clock period definitions
       constant Clk_period : time := 10 ns;
     
    BEGIN
     
        -- Instantiate the Unit Under Test (UUT)
       uut: register_file PORT MAP (
              src_s0 => src_s0,
              src_s1 => src_s1,
              des_A0 => des_A0,
              des_A1 => des_A1,
              Clk => Clk,
              data_src => data_src,
              data => data,
              reg0 => reg0,
              reg1 => reg1,
              reg2 => reg2,
              reg3 => reg3
            );

       -- Clock process definitions
       Clk_process :process
       begin
            Clk <= '0';
            wait for Clk_period/2;
            Clk <= '1';
            wait for Clk_period/2;
       end process;
     

       -- Stimulus process
       stim_proc: process
       begin       
       
            data <= "0101010101010101";
           
                src_s0 <= '0'; src_s1 <= '0';
                des_A0 <= '0'; des_A1 <= '0';
               
                wait for 10 ns;
                    des_A0 <= '1'; des_A1 <= '0';
                   
                wait for 10 ns;
                    des_A0 <= '0'; des_A1 <= '1';
                   
                wait for 10 ns;
                    des_A0 <= '1'; des_A1 <= '1';
                   
               
            wait for 10 ns;
                data <= "0000111100001111";
               
                wait for 10 ns;
                    des_A0 <= '1'; des_A1 <= '0';
                   
                wait for 10 ns;
                    des_A0 <= '0'; des_A1 <= '1';
                   
                wait for 10 ns;
                    des_A0 <= '1'; des_A1 <= '1';
           
           
            ----
           
            data <= "0101010101010101";
           
            wait for 10 ns;
                src_s0 <= '1'; src_s1 <= '0';
                des_A0 <= '0'; des_A1 <= '0';
               
                wait for 10 ns;
                    des_A0 <= '1'; des_A1 <= '0';
                   
                wait for 10 ns;
                    des_A0 <= '0'; des_A1 <= '1';
                   
                wait for 10 ns;
                    des_A0 <= '1'; des_A1 <= '1';
                   
           
            wait for 10 ns;
                data <= "0000111100001111";
               
                wait for 10 ns;
                    des_A0 <= '1'; des_A1 <= '0';
                   
                wait for 10 ns;
                    des_A0 <= '0'; des_A1 <= '1';
                   
                wait for 10 ns;
                    des_A0 <= '1'; des_A1 <= '1';
               
            ----   
               
            data <= "0101010101010101";
               
            wait for 10 ns;
                src_s0 <= '0'; src_s1 <= '1';
                des_A0 <= '0'; des_A1 <= '0';
               
                wait for 10 ns;
                    des_A0 <= '1'; des_A1 <= '0';
                   
                wait for 10 ns;
                    des_A0 <= '0'; des_A1 <= '1';
                   
                wait for 10 ns;
                    des_A0 <= '1'; des_A1 <= '1';
                   
                   
            wait for 10 ns;
                data <= "0000111100001111";
               
                wait for 10 ns;
                    des_A0 <= '1'; des_A1 <= '0';
                   
                wait for 10 ns;
                    des_A0 <= '0'; des_A1 <= '1';
                   
                wait for 10 ns;
                    des_A0 <= '1'; des_A1 <= '1';
                   
            ----   
           
            data <= "0101010101010101";
           
            wait for 10 ns;
                src_s0 <= '1'; src_s1 <= '1';
                des_A0 <= '0'; des_A1 <= '0';
               
                wait for 10 ns;
                    des_A0 <= '1'; des_A1 <= '0';
                   
                wait for 10 ns;
                    des_A0 <= '0'; des_A1 <= '1';
                   
                wait for 10 ns;
                    des_A0 <= '1'; des_A1 <= '1';
                   
       
            wait for 10 ns;
                data <= "0000111100001111";
               
                wait for 10 ns;
                    des_A0 <= '1'; des_A1 <= '0';
                   
                wait for 10 ns;
                    des_A0 <= '0'; des_A1 <= '1';
                   
                wait for 10 ns;
                    des_A0 <= '1'; des_A1 <= '1';

         -- wait;
       end process;

    END;
     

    Am I going in the right way at all with it?
     
  2. jcsd
  3. Feb 25, 2012 #2
    please help me these is my first time on these forum.I didn't know where to post these question.A car and a truck start from rest at the same time, with the car initally some distance behind the the truck. The acceleration of the truck is 2.10m/s^2 and the acceleration of the car is 3.40 m/s^2. The car overtakes the truck after the truck has moved 40.0 m.how long does it takes the car to overtake the truck?

    I tried to equate the distance traveled by both, abd it turns to be is if the car has travelled 40.m
     
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