Vhdl Traffic Signal

  1. hey, i wrote this design in Xilinx of a traffic signal with pedestrain crossing. I am getting this error and have no clue as to what it is...........



    =========================================================================
    * HDL Compilation *
    =========================================================================
    WARNING:HDLParsers:3516 - Found error in file "C:/Documents and Settings/5402050/Desktop/traffic_lights/newproject/trafficsignal.vhd".
    WARNING:HDLParsers:3458 - Because of erroneous VHDL file(s), automatic determination of correct order of compilation of files in project file "C:/Documents and Settings/5402050/Desktop/traffic_lights/newproject/TopLevel_vhdl.prj" may be inaccurate. Please put the files in the project file in correct order with keyword 'nosort' at end of the project file, or compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s).
    Compiling vhdl file "C:/Documents and Settings/5402050/Desktop/traffic_lights/newproject/trafficsignal.vhd" in Library work.
    Entity <traffic> compiled.
    ERROR:HDLParsers:164 - "C:/Documents and Settings/5402050/Desktop/traffic_lights/newproject/trafficsignal.vhd" Line 111. parse error, unexpected PROCESS, expecting IF
    -->

    Total memory usage is 112812 kilobytes

    Number of errors : 1 ( 0 filtered)
    Number of warnings : 2 ( 0 filtered)
    Number of infos : 0 ( 0 filtered)


    Process "Synthesize" failed

    any ideas . i can mail or pm the codes i hv if u want .thanks
     
  2. jcsd
Know someone interested in this topic? Share a link to this question via email, Google+, Twitter, or Facebook

Have something to add?

0
Draft saved Draft deleted