Why does the supply go past pull-downs but electrostatic voltage through pull-down?

[treehouse]

When you use a pull-down resistor (resistor to ground) between a switch and a gate to prevent floating, why does the supply go past the pull-down but electrostatic voltage through the pull-down? Shouldn't it just go through whichever one has less resistance? Is there some kind of 'bandwidth rule' in play here?

 

[yungman]

No idea what you are talking, a drawing would be helpful.

 

[Floid]

As far as I know electostatic voltage would go past the pull-down as well.

 

[treehouse]

As far as I know electostatic voltage would go past the pull-down as well.

The pull-downs keep the gate inputs from floating. This much is obvious in my college's lab.

 

[berkeman]

When you use a pull-down resistor (resistor to ground) between a switch and a gate to prevent floating, why does the supply go past the pull-down but electrostatic voltage through the pull-down? Shouldn't it just go through whichever one has less resistance? Is there some kind of 'bandwidth rule' in play here?

No idea what you are talking, a drawing would be helpful.

The pull-downs keep the gate inputs from floating. This much is obvious in my college's lab.

Well, that's about all that's obvious in this thread so far.

"Why does the supply go past the pulldown?" "but electrostatic voltage through the pulldown?"

I second the request for a diagram, and what do you mean by "past" and "through"? And what ESD voltage?

 

[treehouse]

I second the request for a diagram, and what do you mean by "past" and "through"? And what ESD voltage?

I don't know how to put a diagram here.

A resistor is placed between a switch and a gate input to keep the input from floating when the switch is open. The resistor is connected to the ground rail; v_out is also connected the ground rail. The ground rail is connected to the negative side of the power supply - otherwise the circuit won't be live.

Electrostatic voltage is the voltage resulting from electrostatic interference that causes floating inputs.

 

[berkeman]

I don't know how to put a diagram here.

A resistor is placed between a switch and a gate input to keep the input from floating when the switch is open. The resistor is connected to the ground rail; v_out is also connected the ground rail. The ground rail is connected to the negative side of the power supply - otherwise the circuit won't be live.

Electrostatic voltage is the voltage resulting from electrostatic interference that causes floating inputs.

If the gate's Vout is connected to ground, the gate output will not do much.

The pulldown resistor just sinks whatever bias current there is for the input to the gate. V=IR, so as long as the resistor is small enough (usually about 10k Ohms), that is enough to sink the small input bias current and pull the input down below Vih.

To add attachments, look for the paper clip icon above the posting/advanced-reply dialog box.

 

[yungman]

I don't know how to put a diagram here.

A resistor is placed between a switch and a gate input to keep the input from floating when the switch is open. The resistor is connected to the ground rail; v_out is also connected the ground rail. The ground rail is connected to the negative side of the power supply - otherwise the circuit won't be live.

Electrostatic voltage is the voltage resulting from electrostatic interference that causes floating inputs.

If you have a scanner, scan the drawing into jpg file and make it less than 60 to 80KB. I use:

www.tinypic.com

to upload. Copy the "IMG" link, click the Insert File ( with a paper clip) here and paste the link and wala, you have your drawing. I don't want to answer anything until I see the drawing.

 

[Floid]

Ohh, when you said electrostatic voltage I assumed you meant from ESD or the likes.

 

[treehouse]

The question is raised by us thinking that there is only one path of least resistance for a voltage.

 

[berkeman]

The question is raised by us thinking that there is only one path of least resistance for a voltage.

Current divides among parallel resistances. It is not an all-or-nothing thing, with only the "path of least resistance" sustaining a current when a voltage is placed across multiple parallel resistances.

Still no diagram?

 

[treehouse]

Current divides among parallel resistances. It is not an all-or-nothing thing, with only the "path of least resistance" sustaining a current when a voltage is placed across multiple parallel resistances.

Well, sure I've seen the supply voltage go through multiple gates from a rail too. I'm just wondering why these things happen.

 

[vk6kro]

This depends on source impedance.

For example, a logic chip may have unused inputs and if these are not protected with resistors to ground, or to the supply voltage, the pin may acquire a static voltage because it can have an impedance of hundreds of megohms and it only takes a few electrons to charge its very small capacitance.

Placing even a very high resistance in parallel with the chip's impedance means that it becomes a lot harder to supply these electrons from a static charge and they can drain away through the resistor when the static charging source is removed.

Applying a "proper" drive signal, which has no problem supplying these electrons, drives the input successfully.

Early CMOS chips were reputed to be damaged by finger contact with the pins, so they were supplied in conductive foam or plugged through aluminum foil. Modern ones have internal protection for sensitive input pins.