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peejake
May3-06, 02:45 AM
hey guys,
im new to this posting thing on this site......if any of u belong to bossgtcentral.com, i am xcortman there lol..... Anyway guys i am looking for a program that allows me to enter a boolean expression no matter how complicating it is and i want it to give me the Logic Gate diagram for it>>> If any of u guys could help me with this problem.... BD+AB/D/+AB/C
where + is &.......and / is Not.....Any help will be appreciated>>>
Thankyou
jake
:smile:

berkeman
May3-06, 10:10 AM
I googled palasm free download, and got lots of hits:

http://www.google.com/search?hl=en&q=palasm+free+download

PALASM is an assembler for PALs and CPLDs. You code up your logic in ABLE or Verilog, and it compiles the code and generates the programming file (and the report file) for most PALs and CPLDs.


(EDIT -- The report file is where it will tell you how it has hooked up the logic gates in the PAL you have targeted.)

peejake
May3-06, 08:13 PM
hey berkman,
thankyou ill check it out!!!!!!
PJ

chroot
May3-06, 08:45 PM
My interpretation is that he's looking for a program that will generate a schematic with explicit gate symbols from a given Boolean expression.

- Warren

berkeman
May3-06, 10:29 PM
My interpretation is that he's looking for a program that will generate a schematic with explicit gate symbols from a given Boolean expression.

- Warren
True, but all I could think of was a CPLD compiler. And that only really helps him because of the constrained architecture of CPLDs. I wonder what he wants the generalized compiler for.... And if he doesn't care about how deep his resulting "sea of gates" is, he's going to have to learn about timing constraints and synchronous design, eh? :devil: :biggrin:

peejake
May4-06, 06:29 PM
True, but all I could think of was a CPLD compiler. And that only really helps him because of the constrained architecture of CPLDs. I wonder what he wants the generalized compiler for.... And if he doesn't care about how deep his resulting "sea of gates" is, he's going to have to learn about timing constraints and synchronous design, e

Well Berkeman,

I am not going into any serious designing at the moment....It is just for a bit of irritating homework i get everyother week...:rofl: I just need a program to help me generate a logic gate diagram when i enter the boolean expression....I hope u know what i mean now??????

Oh by the way i tried the program you sent me but nothing happens when i enter the folder and click on install......I must have downloaded the wrong one....
:grumpy:

chroot
May4-06, 08:00 PM
Well, there are some high-level tools that can produce a schematic from a gate-level netlist, which can be generated from RTL by a synthesizer.. but those are big guns (like the $10k a seat Cadence tools here at work). Hardly anyone uses such tools for things like that anyway, except incidentally. I don't know of any small programs that do the same thing; it's just not something one would normally want to do. Most people want to convert their complex views of a circuit into simpler views, not the other way around.

- Warren

peejake
May7-06, 05:42 PM
it's just not something one would normally want to do. Most people want to convert their complex views of a circuit into simpler views, not the other way around.
- Warren

Well it just so happens that my teacher wants me to do the thing the other way round. I think he does this because he wants us to get a sound understanding of the whole concept back to front...Anyway do you know a site that would at least teach me the steps in order to work the thing out>>>???
Thanks

Cheers
jake

chroot
May7-06, 06:26 PM
Unless you're talking about an expression that has hundreds of terms, I don't see any reaon why you'd need software to help you with this.

- Warren

peejake
May7-06, 10:19 PM
Oh well i guess it does not matter anymore. Ill just have to keep looking on google for a tutorial on this topic....

jake