Verilog help

[david90]

my goal is to make a mod 60 counter using mod10 and mod6. Both counters have a clk input.

Mod10 will count and will produce a cout which will carry to mod6. At this moment, mod10 will be 0 while mod6 is 1 which is 10. This will continue to 59.

I need serious help on how to connect them together. For the clk parameter, what should I enter?

[Guybrush Threepwood]

Originally posted by david90
For the clk parameter, what should I enter?

In the testbench? I don't quite understand.....

[chroot]

It would seem the mod 6 counter should be clocked by the overflow of the mod 10 counter.

- Warren