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tcosentino
#1
Dec7-11, 06:14 PM
P: 1
So i am writing a Verilog program for a combination lock. I am using a state machine format to write it. I have commented out everything and just isolated one if statement as you can see. No matter what i put in the if statements the code within it (next_state = Inuse;) activates. The only way i can possibly get that code to not run is if i put in if(0).

I have been trying things and staring at it for a few hours but can not figure it out. Thank you for any help.

Here is my code:

module Lock_Logic(
clk,
clear, reset,
kp, v,
sec_3, sec_5,
lt_Reset, lt_Inuse, lt_Disable, lt_Open, prev_kp,
o_count //for output display
);

input clk;
input clear, reset;
input [3:0] kp;
input v;
input sec_3, sec_5; //high when 3sec or 5sec clock goes off respectively

output lt_Reset, lt_Inuse, lt_Disable, lt_Open; //if used in combo logic add reg
output [1:0] o_count;

//----Define state values as constants----------------
parameter Reset = 3'b001;
parameter Inuse = 3'b010;
parameter Disable = 3'b011;
parameter Open = 3'b100;

//----Internal Variables------------------------------
reg [2:0] state; // registered state value
reg [2:0] next_state; // combinational next state value
output reg [3:0] prev_kp;
reg [1:0] cnt;

//----Initial values----------------------------------
initial
begin
next_state = Reset;
prev_kp = 15;
end

//----------------------------------------------------
// Combinational logic to determine next state and outputs
//
always @ (state, clear, v)
begin
if(clear)
begin
// case (state)
// Reset: //reset case
// Inuse: //inuse case
// Disable: //disable case
// Open: //open case
// endcase
end
if(kp != prev_kp)
next_state = Inuse;
// begin
// case (state)
// Reset: //reset case
// begin
// next_state = Inuse;
// end
//// Inuse: //inuse case
//// Disable: //disable case
//// Open: //open case
// endcase
// end
prev_kp <= kp; //to check if the number pressed has changed
end

//----Sequential logic to register the state value----
always @ (posedge clk)
state <= next_state;

//----Output Logic------------------------------------
assign lt_Reset = (state == Reset) ? 1 : 0;
assign lt_Inuse = (state == Inuse) ? 1 : 0;
assign lt_Disable = (state == Disable) ? 1 : 0;
assign lt_Open = (state == Open) ? 1 : 0;
assign o_count = cnt;
endmodule
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