|Jun23-12, 02:41 PM||#1|
Up/Down synchronous counter
I'm wondering if someone could explain why when trying to make a 3 bit up/down counter using T flip flops, there are two and gates connected to the final multiplexer ?
Can someone explain how you approach this?
And same with the JK Flip flop but with an xor gate.
I'm really confused on how you come up with this.
|Jun23-12, 07:20 PM||#2|
When doing a Google search on "3 bit up/down counter using T flip flops" it appears to be a homework problem. May I suggest you Google search those many sites and find your answers there?
|Jun27-12, 06:41 PM||#3|
When we are doing the excitation table for counters...why is the W=0 for the next state not included?
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