Draw Logic Gates: Find a Program to Create Gate Diagrams

In summary, Jake is looking for a program that will generate a schematic with explicit gate symbols from a given Boolean expression. He has unsuccessfully tried a CPLD compiler and a high-level tool. He is grateful for a suggestion to try a site that might teach him how to do this.
  • #1
peejake
69
0
Drawing Logic Gates!

hey guys,
im new to this posting thing on this site...if any of u belong to bossgtcentral.com, i am xcortman there lol... Anyway guys i am looking for a program that allows me to enter a boolean expression no matter how complicating it is and i want it to give me the Logic Gate diagram for it>>> If any of u guys could help me with this problem... BD+AB/D/+AB/C
where + is &...and / is Not...Any help will be appreciated>>>
Thankyou
jake
:smile:
 
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  • #2
I googled palasm free download, and got lots of hits:

http://www.google.com/search?hl=en&q=palasm+free+download

PALASM is an assembler for PALs and CPLDs. You code up your logic in ABLE or Verilog, and it compiles the code and generates the programming file (and the report file) for most PALs and CPLDs.


(EDIT -- The report file is where it will tell you how it has hooked up the logic gates in the PAL you have targeted.)
 
  • #3
hey berkman,
thankyou ill check it out!
PJ
 
  • #4
My interpretation is that he's looking for a program that will generate a schematic with explicit gate symbols from a given Boolean expression.

- Warren
 
  • #5
chroot said:
My interpretation is that he's looking for a program that will generate a schematic with explicit gate symbols from a given Boolean expression.

- Warren
True, but all I could think of was a CPLD compiler. And that only really helps him because of the constrained architecture of CPLDs. I wonder what he wants the generalized compiler for... And if he doesn't care about how deep his resulting "sea of gates" is, he's going to have to learn about timing constraints and synchronous design, eh? :devil: :biggrin:
 
  • #6
berkeman said:
True, but all I could think of was a CPLD compiler. And that only really helps him because of the constrained architecture of CPLDs. I wonder what he wants the generalized compiler for... And if he doesn't care about how deep his resulting "sea of gates" is, he's going to have to learn about timing constraints and synchronous design, e

Well Berkeman,

I am not going into any serious designing at the moment...It is just for a bit of irritating homework i get everyother week...:rofl: I just need a program to help me generate a logic gate diagram when i enter the boolean expression...I hope u know what i mean now?

Oh by the way i tried the program you sent me but nothing happens when i enter the folder and click on install...I must have downloaded the wrong one...
:grumpy:
 
  • #7
Well, there are some high-level tools that can produce a schematic from a gate-level netlist, which can be generated from RTL by a synthesizer.. but those are big guns (like the $10k a seat Cadence tools here at work). Hardly anyone uses such tools for things like that anyway, except incidentally. I don't know of any small programs that do the same thing; it's just not something one would normally want to do. Most people want to convert their complex views of a circuit into simpler views, not the other way around.

- Warren
 
  • #8
chroot said:
it's just not something one would normally want to do. Most people want to convert their complex views of a circuit into simpler views, not the other way around.
- Warren

Well it just so happens that my teacher wants me to do the thing the other way round. I think he does this because he wants us to get a sound understanding of the whole concept back to front...Anyway do you know a site that would at least teach me the steps in order to work the thing out>>>?
Thanks

Cheers
jake
 
  • #9
Unless you're talking about an expression that has hundreds of terms, I don't see any reaon why you'd need software to help you with this.

- Warren
 
  • #10
Oh well i guess it does not matter anymore. Ill just have to keep looking on google for a tutorial on this topic...

jake
 

1. What are logic gates and why do we need to draw them?

Logic gates are basic building blocks of digital circuits. They are used to perform logical operations, such as AND, OR, and NOT, on binary inputs to produce a binary output. Drawing logic gates helps us visualize how these operations are performed and how the circuit works.

2. Is there a specific program for creating gate diagrams?

Yes, there are several programs available for creating gate diagrams, such as Logic Gate Simulator, Digital Logic Design, and Logisim. These programs offer a user-friendly interface and a wide range of logic gates to choose from for creating accurate and detailed diagrams.

3. Do I need to have programming experience to use these programs?

No, most logic gate diagram programs have a drag-and-drop interface, making it easy for anyone to use, regardless of programming experience. Some programs also offer tutorials and guides to help beginners get started.

4. Can these programs simulate the logic gates and circuits?

Yes, most programs have a simulation feature that allows users to test and verify the functionality of their logic gates and circuits. This is a useful tool for troubleshooting and debugging before implementing the circuit in real life.

5. Are these programs free to use?

Some programs offer a free trial or limited version for users to try out, but most fully-featured logic gate diagram programs require a purchase or subscription. However, there are also free and open-source options available for those on a budget.

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