Etching of SOI wafer


by Excom
Tags: etching, wafer
Excom
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#1
Nov28-08, 04:19 AM
P: 44
Hi

I am trying to make a Si nanowire MOSFET and in this process I have to etch the toplayer of a SOI wafer.

I have made some reactive ion etching (RIE) experiments on Si wafers and obtained an etch rate of 550 nm/min. SF6 have been used as the feedstock gas.

However, when trying to etch the to Si layer on a SOI wafer the etch rate is reduced to 10 nm/min. Is there anyone that can explain this lowering of the etch rate when going form a Si wafer to a SOI wafer? Or is there anyone that have a good recipe for RIE etching of SOI wafers?
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Mapes
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#2
Nov28-08, 09:59 AM
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I wonder if charging of the top layer is affecting the etch process. What's your biasing setup (e.g., DC, RF)?

CF4 is another very common etch gas for silicon, but you may encounter the same problem.
Excom
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#3
Nov28-08, 12:50 PM
P: 44
I am using a RF plasma.

I will try to exchange the SF6 with CF6 and see what happens.

Thanks for your help.

Mapes
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#4
Nov28-08, 03:56 PM
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Etching of SOI wafer


Hmm, RF should get around any problems with non-conductive layers. The buried oxide is somewhat of a thermal insulator, but that should only speed up etching if the top silicon layer is getting hotter than a regular wafer would. I'm stumped.

Maybe the CF4 will work well, and in any case it's good experience to try another etch recipe. Usually some oxygen is added to react with any deposited carbon. Hopefully a characterized recipe already exists for your tool.
L62
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#5
Dec17-08, 11:58 PM
P: 31
are you using RIE or DRIE (passivation steps)?
Excom
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#6
Jan6-09, 07:03 AM
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I am using RIE
Mapes
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#7
Jan6-09, 08:39 AM
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Any progress?
L62
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#8
Jan7-09, 08:36 PM
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the lowering of the etch rate could be due to a change in thermal conductivity since now the flim is on a different substrate and the oxide has a lower thermal conductivity. did your etch geometry change? etch rate also changes with geometry of exposed area due to the loading effect.
Excom
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#9
Jan23-09, 04:36 AM
P: 44
I have had no progress with the etching.

One solution could be that I try to use a ICP RIE system instead of a RIE system.

Lower thermal conductivity. Why should a lower thermal conductivity result in a lower etching rate? A higher temperature will probably only increase the etch rate or is there something that I am not aware of?

The geometry that I am trying to etch on the SOI wafer is the same as the one on the SI wafer.


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