NEW Microcontroller Hardware Architecture Design (Was it a beneficial thing to try?)

Mastermind_14

Hi people!

I am a student of Electrical engineering (5th semester) and have a profound interest in HDL (ie. verilog) Programming. For my 5th semester project of Digital System Design i have designed and implemented a primitive microcontroller Hardware architecture from scratch having.......

>All 2 byte instructions
>128 byte ROM
>63 different instructions including Jumps,call/return,push/pop ,CJNE, DJNZ etc(most of 8051 and PIC18f452)
>ALU, ROM and Processor are seperate modules inside the main module "IC"
>16 byte deep stack
>8 byte of byte addressible RAM
>1 byte of bit addressible RAM
>Time shared architecture of busses
>Machine cycle of 1 clock cycle
>and many more

This hardware architecture that i have thought of and implemented in Verilog with greatest level of detail was completed in just 2 weeks with little effort which made me eager to explore this HDL even more and pick even more challenging projects. so if you can guide me to some challenging project or want to know about this microcontroller implementation in verilog then please PM me or post to this thread.

Furthermore does this project of mine has any more significance then just serving my academic purposes? If yes then what is the significance? and if no then in what direction should i spend my HDL programming skills such that I might get some recognition ( credited for doing something unique and useful )?

NOTE: An image of the Instruction architecture has also been uploaded to give a vague idea of what I am saying.

Attached Thumbnails

 

Phrak

You can look into things such as instruction pipelining, datablock moves, high level language hardware layer, intelligent branch select opcode prefetch, risc and parallelism, aisc, dsp architecture, harvard architecture, memory control.

Mastermind_14

Dear Phrak,

First of All thanks for your reply.Now the thing is that I have already employed

>risc and parallelism
>harvard Architecture
>datablock moves
>memory control

While I did not find any use of

>instruction pipelining
>intelligent branch select opcode prefetch

This is because I designed and implemented the architecture in a HDL with no intention of implementing it on FPGA (unless it is worth implementation) so I designed it such that the input and output data throughout the microcontroller is multiplexed on negative level and positive level of the clock respectively. So this cannot be optimized more then a single clock cycle while every process is completed with just zero time delay and pipelining would mean adding latency for no increase in clock speed. Same is the case with prefetching of opcode.

Though I find aisc and dsp architecture the next fields that I should explore so thanks for this suggestion.

I want to know a few more things.

>The main question remains unanswered "Does this project of mine has any more significance then just serving my academic purposes?"

>Is Verilog being currently employed to implement and simulate microcontroller architectures in the Industry? If yes then which companies are doing this?

Phrak

It wasn't apparent from you initial post what all you'd been doing. I'd though perhaps a bare bones micro, and so the seggestions for what you might persue. I haven't done any of this in 15 years, so I'm out of this loop, but there are all kinds of games you can play with the clock. The external clock can drive an internal frequency multiplier, so that you can generate multiple internal clocks with edges just about anywhere you want them.

What your doing should give you some background if you intend to persue a CE. I hope someone else has better answers than I.

Mastermind_14

I didnt understand what you mean by

Can you please elaborate it.

Phrak

I re-read your first post. I see you are an EE student, rather than CE. Either way, it should serve just as well. But next time you speak to an engineer, ask him of what he learned in school applies to his current job.