In VHDL, what is strongly typed means?

by dexterdev
Tags: means, strongly, typed, vhdl
dexterdev is offline
Mar20-13, 12:21 AM
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In VHDL, what is strongly typed means? ie like VHDL is a strongly typed language etc

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SteamKing is offline
Mar20-13, 12:43 AM
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the_emi_guy is offline
Mar20-13, 01:21 AM
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Strongly typed means that the compiler enforces lots of constraints on how different data types can be intermixed and what operations can be performed on them. Compile errors are produced if an attempt is made to mix incompatible data types, or perform operations on improper data types. In contrast, loosely coupled means that one is free to mix data types and the programmer is responsible for knowing how the compiler will interpret the resulting operation.

Here is a rather extreme example: what happens if I attempt to perform the operation of multiplication on two character string data types? A strongly typed language will produce an error, after all it makes no sense to multiply character strings right?

On the other hand, a loosely typed language may go ahead and multiply them according to some predetermined rule that the programmer is expected to be aware of. JavaScript can be considered loosely typed in this respect. "12"x"12" will produce the character string "144" while "12"+"12" produces "1212" since + happens to be the concatenation operator for strings.

Back to VHDL: same idea. I cannot assign a 4-bit variable to an 8-bit register. They are considered incompatible and a compile error will result. Verilog, which is weakly typed, will make the assignment and we developers are fully aware of how the 4-bits will get mapped to the 8-bit register. Same the other way around. If I assign an 8-bit variable to a 4-bit register, Verilog developers know which 4 bits are getting truncated. VHDL programmers will get a compile error.

Windadct is offline
Mar21-13, 03:02 PM
P: 534

In VHDL, what is strongly typed means?


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