Recent content by coolmoniker

That's the difficulty...The book states that Ci can be found in 2 logr(n) + 1 delays, where r is the number of inputs for each gate. So for 2 inputs and 4 bits, that's 5 delays. Apparently it's possible, but I can't do it in less than six. There must be some trick or logic identity to exploit.

Homework Statement I have a book which says that the gate delay for generating Ci is 2 logr(n) + 1, where r is the fan-in for each gate and n is the number of bits. This implies that with a fan-in of 2 and 4 bits, the delay for a generating C5 as shown below should be 5 gate delays. How...