Recent content by ShreyasR

I am trying to understand how the input impedance of a bootstrapped darlington emitter follower is analysed. They make use of Miller's theorem. But honestly, I have not understood this theorem as well... All I know is bootstapping increases input impedance but i have no clue as to how? And why...

That sounds like a convincing answer! Thanks Dave! :smile:

someone Please reply... I promise this will be my last question... my practical exam is nearning and i want to be prepared with an answer for this question...

Someone please correct me if I am wrong... Is my understanding of this concept just fine? This will be the last question...

So SL100, CL100, SK100 and CK100 are transistors which do not follow these standard naming conventions which are there, isn't it? So in my Analog electronics Laboratory viva, If they ask me something about components which follow european standard of naming or american standard of naming, I can...

In my college, we used this transistor named SL100 and another one named CL100 for various experiments. But why are they named that way? I browsed the net for an answer for almost an hour but couldn't find a proper answer to this? What does S and L mean? what does 100 mean? From the Datasheets...

Could you find a solution to this integral?

Hi! :smile: The amplitude of the carrier is EC. This is the base amplitude of the carrier. when it is modulated with a modulating signal eM, It's amplitude is changing according to the instantaneous value of eM. Have a look at the waveforms: Vam = [Ec + Emcos(ωmt)]cos(ωct) In...

You can follow this method to redraw any circuit. (1) Mark all the nodes using notations of your choice. (2) Then start redrawing by marking these nodes in a different manner such that, when you connect the components back, you obtain a planar circuit! (3) If you find two or more nodes such...

I can see four nodes in this circuit. Mark those nodes as A, B, C, D starting from the top in clockwise direction. like this: Now redraw the circuit by first marking the nodes A, B, C, D one below the other. Then connect the components between the nodes in such a way that you get a planar...

Exactly... So for analysis, one must consider both cases: potentials across them are equal, and currents through them is same!

Oh my! Thank you NascentOxygen and The Electrician... I made a mistake in marking Iout... It is the current flowing through the load and not through hoe... Well now i get it all... Now i guess i get a clear picture of two port networks. This is how I have understood it: For any linear two port...

Iout = h21Iin + h22Vout this is the relation between Iout and Vout (Equation 2)

Sorry. I thought that made sense but then i landed up in this situation. When i connect a signal generator to the input, all that i know is Vin, and the h parameters. So how do i theoretically calculate 3 unknowns (Vout, Iin and Iout) when i have only two equations from the h parameters? I...

Sorry. I thought that made sense but then i landed up in this situation. When i connect a signal generator to the input, all that i know is Vin, and the h parameters. So how do i theoretically calculate 3 unknowns (Vout, Iin and Iout) when i have only two equations from the h parameters? I...