Dear, rakeshgarg123
Unfortunately, I don't know the test circuit exactly
I used HP4156A analyzer and default setting for FET.
SiO2 thickness is 100 nm.
Is this not enough to understand my problem?
Thanks for your comment, es1.
the attached picture shows the device.
(my goal is to get electrical characteristics for N-type semiconductor)
I believe that 'source' acted as a common electrode but I'm not sure I drew the connections between gate-source and drain-source correctly because I...
Hi,
I fabricated a very simple back-gate FET.
I used highly Boron doped (so, P-type) Si wafer as a gate and then, grown SiO2 thermally as a dielectric. And, deposited N-type semiconductor followed by Au/Cr deposition as electrodes (source and drain).
And I measured Ids-Vds and Ids-Vg. The...