T Flip-Flop Using A D Flip-Flop HDL?

[pags920]

I am trying to figure out how to make a T Flip Flop using a D Flip-Flop. I know that I need to use a XOR gate in order to make the T Flip-Flop, but I am having trouble putting it into a Verilog code. Below is the module for the flip-flop. Do I have to create a new module just for the XOR gate or can I incorporate it somehow in the flip flop module?


module T_flip_flop (Q, D, CLK, Clr);
output Q;
input D, CLK, Clr;
reg Q;

always @ (posedge CLK or negedge Clr)
if(~Clr)Q<=1'b0; else Q<=D;
endmodule

[Antiphon]

I don't know verilog but a D flip flop outputs whatever is at the D input when you clock it.

If you want it to toggle, wire D to bar(Q).