Ring Oscillator

[littlebilly91]

I am doing a discrete event simulation of logic gates and I have come upon a problem. I have set up a system similar to a ring oscillator. I understand that this system should not oscillate, but after thinking about it, I'm not sure why not. The system has one input, 1 fed into a NAND gate. The NAND feeds into a NOT and the not feeds back into the original NAND. This is similar to an even number of NOTs so it shouldn't oscillate, but any time I analyze it step by step it seems like it still would. Here is my thinking:

At time 0:
Both gates output a 0.
The NAND sees a 1 from the output and a 0 from the NOT gate
The NOT sees a 0 from the NAND
Both the NAND and the NOT will switch to 1 after a propagation delay.

After one delay:
Both gates output a 1.
The NAND sees a 1 from the output and a 1 from the NOT gate
The NOT sees a 1 from the NAND
Both the NAND and the NOT will switch to 0 after another propagation delay.

repeat forever...

I assumed the delays are the same, is that where the mistake lies? The digital logic class I am in is solely focused on the logic so I don't really know any different.

[vk6kro]

Suppose you had two inverters with each output feeding the input of the other.

Start at one input and assume it is high.
Its output will be low and so will the input it is connected to.

So the second output will be high, which is OK because it is connected to the first input which we assumed was high.

So, this is a stable state.

Such setups tend to be unstable, though, and may give brief bursts of oscillation ("ringing") if it is driven by another signal.

If you connect a resistor across one of the inverters (from input to output) , and a capacitor in series with either output to input connection, then you will possibly get oscillation. This is a common and useful oscillator.

[littlebilly91]

Right, it makes sense to think about it like that, but to actually simulate it, I need an initial condition. I had previously been considering all gates to initially be at 0. But this seems to give rise to the problem I stated earlier:


At time 0:
Both gates output a 0.
The NAND sees a 1 from the input and a 0 from the NOT gate
The NOT sees a 0 from the NAND
Both the NAND and the NOT will switch to 1 after a propagation delay.

After one delay:
Both gates output a 1.
The NAND sees a 1 from the input and a 1 from the NOT gate
The NOT sees a 1 from the NAND
Both the NAND and the NOT will switch to 0 after another propagation delay.

mistyped it a bit the first time (had output instead of input) Sorry.

[vk6kro]

It looks like a classic race condition.

If both inverters start off with their inputs low and there are pull-up resistors, one of them will get to the "high" level before the other because of small differences in the inverters.

When it does, it will send its output low and force the input of the other inverter to abandon its race upwards and go low.

So, there will be no oscillation, but a couple of glitches on startup.

Unfortunately, simulators do have perfectly matched components, so it would be necessary to deliberately add a resistor or two to produce a realistic difference between components.

[littlebilly91]

Hmmm... that is interesting. I was hoping to be able to resolve this in my simulation. I guess I won't be able to. I am just doing a simple logic sim, and it's not really fit to handle things like this. Thanks for the feedback. PF never lets me down!