Semiconductor process corner

[likephysics]

What exactly is a process corner. Is it actually the corner on the silicon wafer?
Why does speed vary in process corners?
Is the doping not uniform?

[phyzguy]

No, it's not the corner of the wafer. It is a model of the process which attempts to capture the extremes of the distribution of the process. Think of it this way. Say I process a large number of chips across different wafers. There will be a distribution of speeds in those chips, because process variables like oxide thickness, effective channel length, doping concentration, etc. have statistical distributions. There will then be a mean and a standard deviation associated with this speed distribution. The typical process model is supposed to model the mean speed that you would expect to see, and the process corner models are supposed to capture some variation from the mean. Whether it is a 2-sigma variation from the mean, a 3-sigma variation from the mean, or something else depends on how the models are constructed and how your circuit is designed. It is called a "corner" because if I make a plot of several process variables (for example Tox and Leff), then the corner model is usually from the corner of this 2D plot.

To answer your question about doping uniformity, the answer is no, the doping is not perfectly uniform. Any manufacturing variable in the real world is not perfectly controlled and has a statistical distribution associated with it. Even if the process tools are perfect (and they're not), there are statistical variations of things like the number of atoms in each transistor which are inherently random.

[likephysics]

It is called a "corner" because if I make a plot of several process variables (for example Tox and Leff), then the corner model is usually from the corner of this 2D plot.


Thanks. I have a better understanding now.
But I still did not get the "corner" explanation. Little more detail please.
Are you trying to say the extremes of the plot?

If I have a FF and SS corner. What effect will temperature have on corners.
Will FF become more fast and SS more slow?

[phyzguy]

Attached is a drawing showing, for example, NMOS and PMOS speed with FF, SS, FS, amd SF corners. Yes, temperature is typically on top of this. Digital logic tends to slow down as it gets hotter, so a (S,S,Hot) corner will typically be slower than a (S,S,Room) corner. However, different circuits respond differently, so you usually have to run all process and temperature corners to determine which is the slowest. Also, people tend to think that the faster corners are always better, but some circuits can be too fast at the fast corners (if your circuit has race conditions for instance). Analog circuits tend to have problems at FS and SF corners where device matching can be compromised.

[likephysics]

Thanks. Now I am more informed.

[jsgruszynski]

A lot of this also comes down to process control variances. A corner will be your worst case for maintaining production quality but some corners have greater sensitivity than others. Related to Design of Experiment also.