Using GCC to generate makefile dependencies.

[TylerH]

How do I use GCC to generate dependencies for makefiles? I tried using the -M option, like below, but I don't know how to insert the name of the .cpp into the shell command that calls GCC with the -M option.

%.cpp : $(shell gcc -M $<)

Instead of the desired effect, $< is replaced by nothing, causing GCC to generate an error and my attempt to generate dependencies to fail.

[s09]

I had the same problem that you do now. For that I did some googling around and found a set of tools called Autotools. Here is a pretty good explanation of what you might want to do:

http://www.freesoftwaremagazine.com/books/autotools_a_guide_to_autoconf_automake_libtool

This requires some effort to setup correctly (depends on the complexity of your compilation environment), so if you have only a small number of libraries, hard-coding would be a better option.

What operating system are you using? What libraries are you trying to use?