|Jan3-12, 12:41 AM||#1|
Using GCC to generate makefile dependencies.
How do I use GCC to generate dependencies for makefiles? I tried using the -M option, like below, but I don't know how to insert the name of the .cpp into the shell command that calls GCC with the -M option.
%.cpp : $(shell gcc -M $<)
|Jan16-12, 09:30 PM||#2|
I had the same problem that you do now. For that I did some googling around and found a set of tools called Autotools. Here is a pretty good explanation of what you might want to do:
This requires some effort to setup correctly (depends on the complexity of your compilation environment), so if you have only a small number of libraries, hard-coding would be a better option.
What operating system are you using? What libraries are you trying to use?
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