AND gate


by sandy.bridge
Tags: gate
sandy.bridge
sandy.bridge is offline
#1
Feb3-12, 02:26 PM
P: 767
Why is it required to have 6 transistors? Can it not have 4? Can the output not receive two LOW signals at once? Or does it have something to do with superposition such that upon adding the two signals it may enter the noise margin?
Here, I added a photo.
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phyzguy
phyzguy is offline
#2
Feb3-12, 07:17 PM
P: 2,070
The circuit you've drawn in the bottom doesn't work. You can't use NMOS devices to pull up (and PMOS devices to pull down) in this way, because the devices will turn off before they pull up (or down) all of the way. Suppose your a and b are at Vdd. When those two NMOS devices try to pull up the output it will stop at <Vdd-2*Vt, because the NMOS devices turn off. In practice, what's called the body effect will make it even worse. If Vdd=5V, for example, the output probably won't pull up much past ~3V. Then if you feed this into the next gate of the system, the next NMOS devices have a lower voltage on their gates so the output pulls up less. Bottom line - it doesn't work this way.


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