Electronics - Flip-Flop D

NascentOxygen

Hi FP! Confusion creeps in when you turn your back on a topic for a few weeks.
Yes, "ours" is negative-edge triggered, so the rising edge of the clock has no significance.
Who says so? There is not really a "no change" input condition for the D.
Yes, "we" changed Q to 1 because D was 1 at the crucial moment of the clock transitioning 1→0.

Review the D flip-flop here, though it's positive-edge triggered. http://www.doctronics.co.uk/4013.htm

I like Serena

Finally I have some time again to respond.
Sorry to keep you waiting.


Ah, careful there.
You don't really have a "normal" truth table there with CLK being 0 or 1.

What they mean with CLK=1 is that the clock pulse "triggers".
And a trigger is that the clock pulse is on its edge.
In your new problem statement that is when the clock pulse rises.
At all other times it counts as CLK=0.



The first dotted line is a rising edge.
In the original problem statement that is not the trigger, so that counts as CLK=0.

At the second dotted line we have D=1 and we have a trigger since the clock pulse triggers on the falling edge.
So that counts as CLK=1!

Femme_physics

Ahh the truth table for "rising edge" and "falling edge" helped explain everything to me...

I basically only look at the places where it increases or falls (depends whether it's falling or rising) and then look at the corresponding truth table and bob's your uncle :)

Thanks Nascent, ILS! Though the test is behind me, I thought I aced it except possibly one issue (or two) that bothers me a bit (it's in electrical engineering forum).

I like Serena

Hey Fp!

Any tests left?
Or are you done for a while?

Femme_physics

Hi ILS!

Oh the big external electronics test is still ahead :) do u mind answering my Q at elecrical engineering forum with the PNP transistor? ( not in HW section )

I like Serena

Okay, I'll take a look (didn't notice you posting it).
Give me a minute... (or two ;)