Designing a Counter for 0-5-2-7-4-1-6-3-0 Using Gates and T-Flip Flops

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SUMMARY

The discussion focuses on designing a counter that sequentially counts through the states 0, 5, 2, 7, 4, 1, 6, 3, and back to 0 using T-flip flops and logic gates. Key steps include creating a state table to define the transitions and treating the counter as an n-bit state machine. Participants recommend consulting Rafi's book for similar examples and emphasize the importance of minimizing gate usage for efficiency.

PREREQUISITES
  • Understanding of T-flip flop operation
  • Knowledge of state machine design principles
  • Familiarity with logic gate minimization techniques
  • Ability to create and interpret state tables
NEXT STEPS
  • Study the design of state machines in digital circuits
  • Learn about T-flip flop configurations and applications
  • Explore logic gate minimization methods, such as Karnaugh maps
  • Review examples of similar counter designs in Rafi's book
USEFUL FOR

Electrical engineers, digital circuit designers, and students learning about sequential logic circuits will benefit from this discussion.

vptran84
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hi,

can someone give me hints on how to design a counter that counts
0->5->2->7->4->1->6->3->0 using T-flip flop and some gates? I've been looking at this problem but i don't know where to start...

thanks

vinh
 
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look in rafi's book. There is an example that is very similar to this question. Just follow the steps and the answer will come out. No thinking necessary.

Start by drawing a state table of the counter then find ff input.
 
Don't think of it as a counter, think of it as an n-bit state machine. Then, just assign the states to the numbers you want. The rest is just minimization or consistency (whatever your preference) of gates (assuming you're just going to use those 14 pin gate packages).
 

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