Regarding jk flip flop Q' stability.

In summary, the conversation discusses how to analyze and understand JK flip flops using RS flip flops with NOR gates. The individual is trying to determine the state of Q' when Q = 1, J = 1, and K = 0, and observes that Q' oscillates between 0 and 1 while Q settles to 1. They question the necessity of Q' in JK flip flops and why textbooks often do not mention it. The solution is suggested to use a master slave JK flip flop to prevent oscillation.
  • #1
nascentmind
52
0
Hi,

I am trying to understand and analyze JK flip flop's (using RS flop flop i.e. using NOR gates). I have written out the characteristic table and when I give Q = 1, J=1 and K = 0 I am trying to analyze the Q' (Q complement) by giving the intial state to 0. I find that Q settles to 1 (i.e. Q(t+1)) but Q' oscillates between 0 and 1. How is this fixed? Is the Q' needed in JK flip flops? Also why do textbooks don't talk about Q' in JK or D or T but only Q and Q(t+1) ?

Thanks.
 
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  • #2
J-K-Flip-Flop.jpg


No it won't oscillate for Q=1, J=1, K=0. AND gate with i/p K will always be 0 and AND gate with i/p Q' will always be 0, making FF to hold its state.

However, for J=1, K=1, If the clock enable time is larger than Q/Q' to R/S delay the circuit will oscillate. To resolve the problem use master slave JK FF.
 

1. What is a JK flip flop?

A JK flip flop is a type of sequential logic circuit that is used to store a single bit of data. It has two inputs, J (set) and K (reset), and two outputs, Q (output) and Q̅ (inverse output).

2. How does a JK flip flop work?

A JK flip flop works by using a clock signal to synchronize the inputs and outputs. When the clock signal is high, the inputs are captured and the outputs are updated based on the inputs. The flip flop will either set or reset its output depending on the values of the J and K inputs.

3. What is the stability of a JK flip flop Q output?

The stability of a JK flip flop Q output refers to the ability of the flip flop to maintain a constant logic state without any external inputs. In other words, once the Q output is set or reset, it should remain in that state until a new input is received.

4. How can the stability of a JK flip flop Q output be affected?

The stability of a JK flip flop Q output can be affected by various factors such as noise, improperly timed inputs, and temperature changes. These can cause the flip flop to change states unintentionally, leading to instability in the Q output.

5. How can the stability of a JK flip flop Q output be improved?

The stability of a JK flip flop Q output can be improved by using proper circuit design techniques, such as adding noise filters and using appropriate clock signals. Additionally, using flip flops with higher tolerances and temperature stability can also help improve stability.

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