# Electronics - Flip-Flop D

by Femme_physics
Tags: electronics, flipflop
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 PF Gold P: 2,551 1. The problem statement, all variables and given/known data In the following drawing is given a intro signal to flip-flop type D, negative edge triggered. Also is given the clock pulse signal. Copy to your notebooks these signals and add intro signal Q. Presume that in starting condition Q=0. Also, neglect the delay times of the flop-flop Mine is the pencil of course. Does it make sense?
 HW Helper P: 6,189 Hi! Q remains 0 until the Cp pulse goes down. At that time Q becomes and stays 1 (since the D signal is 1 at that time). The D flip-flop stores the D signal at the negative edge of the clock pulse. This means that when the clock pulse (Cp) goes down, the Q state changes. Q becomes the state of the D signal at that time.
PF Gold
P: 2,551
Alright, as per your criticism...

 The D flip-flop stores the D signal at the negative edge of the clock pulse.
What exactly is the negative edge of the clock pulse? Oh, you mean like when an AC current reaches negative current?

HW Helper
P: 6,189
Electronics - Flip-Flop D

 Quote by Femme_physics What exactly is the negative edge of the clock pulse? Oh, you mean like when an AC current reaches negative current?
The negative edge is where the clock pulse goes down (negative slope), which is the right side of the pulse.
AC current does not have a sharp edge like that.

The only place where Q can change is at that edge.
 HW Helper Thanks PF Gold P: 7,718 From my hobby days I seem to recall that D flip-flops are rising edge triggered. Do they make them both ways now?
HW Helper
P: 6,189
 Quote by LCKurtz From my hobby days I seem to recall that D flip-flops are rising edge triggered. Do they make them both ways now?
According to wiki:
"The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock)."

Wiki seems to imply they are made both ways.
And the problem statement says it's the falling edge.
PF Gold
P: 2,551
 Quote by I like Serena The negative edge is where the clock pulse goes down (negative slope), which is the right side of the pulse. AC current does not have a sharp edge like that. The only place where Q can change is at that edge.
But the graphs only have positive edge?
HW Helper
P: 6,189
 Quote by Femme_physics But the graphs only have positive edge?
What do you mean by positive edge?

The graphs have both positive edges and negative edges.
Each pulse starts with a positive edge, also called the rising edge.
And each pulse ends with a negative edge, also called the falling edge.
 PF Gold P: 2,551 But I have both D and CP for reference. Now I know CP is the clock pulse. D is the input. If Q can only change at NEGATIVE clock pulse edge, then I stand by my last diagram
HW Helper
P: 6,189
 Quote by Femme_physics But I have both D and CP for reference. Now I know CP is the clock pulse. D is the input. If Q can only change at NEGATIVE clock pulse edge, then I stand by my last diagram
In your last diagram Q changes at the rising edge of the clock pulse...

EDIT: A negative edge does NOT mean that the signal is negative, but is means that the level of the signal goes down.
HW Helper
Thanks
P: 5,486
 Quote by Femme_physics But the graphs only have positive edge?
The graphs are drawn to appear to have only positive levels, yes. But these waveforms are logic levels, not voltages, so they are never going to have negative levels. Logic is 1 or 0.

The transition from logic 0 to logic 1, denoted 0→1, is termed the "rising edge" or positive edge. When the logic level changes back to 0, the transition 1→0 is termed the "falling edge" or negative edge. (It has nothing to do with + or - voltages.)

Your Q output is so wrong that I suggest you erase it so you don't keep referring back to it, and can start again with a fresh outlook.

:::NEXT LINE EDITED::::
First step, trace the vertical dotted line from each clock pulse's 1→0 tranistion and mark these faintly on the Q graph--these mark the only place where the Q level can change logic levels because you are told that your D flip-flop is negative-edge triggered.
 PF Gold P: 2,551 Is this correct then?
HW Helper
P: 6,189
 Quote by Femme_physics Is this correct then?
Yep!
 PF Gold P: 2,551 Thanks :)
 PF Gold P: 2,551 *bumps* Would my graph be any different if this was a positive edge triggered D-FF flip-flop, and not negative D-FF flip-flop?
 HW Helper P: 6,189 *bump back* Yes. What do you think it would look like?
 PF Gold P: 2,551 I'm actually really confused about my answer from before. According to the truth table of D flip-flops When D = 1 and CLK = 1 then Q = 1 Since ours is negative on the first dotted line we still kept it zero. Ok. On the second dotted line we have D = 1 and CLK = 0 That's "no change" on both Q and Q(capped)...yet we changed Q to "1" digital. Something doesn't add up here.
HW Helper
Thanks
P: 5,486
 Quote by Femme_physics I'm actually really confused about my answer from before.
Hi FP! Confusion creeps in when you turn your back on a topic for a few weeks.
 According to the truth table of D flip-flops When D = 1 and CLK = 1 then Q = 1 Since ours is negative on the first dotted line we still kept it zero. Ok.
Yes, "ours" is negative-edge triggered, so the rising edge of the clock has no significance.
 On the second dotted line we have D = 1 and CLK = 0 That's "no change" on both Q and Q(capped)...
Who says so? There is not really a "no change" input condition for the D.
 yet we changed Q to "1" digital. Something doesn't add up here.
Yes, "we" changed Q to 1 because D was 1 at the crucial moment of the clock transitioning 1→0.

Review the D flip-flop here, though it's positive-edge triggered. http://www.doctronics.co.uk/4013.htm

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