Design does not fit on the chip

[EvLer]

So, yeah... this is an assignment, but i just need some hint:
we need to write an abel program for a combinational logic function with 5 inputs representing integers 0-31, and two outputs M3 and M5, which indicate whether the number is multiple of 3 or 5, respectively.
So, here's my truth_table... and... my design does not fit on the chip (compiler says)! How can i rework this if compiler isn't able to optimize it?

thanks much as always.

EDIT: i should say that i used GAL16V8D, is it possible to use this PLD or do i need to use something like GAL22?

 

[berkeman]

So, yeah... this is an assignment, but i just need some hint:
we need to write an abel program for a combinational logic function with 5 inputs representing integers 0-31, and two outputs M3 and M5, which indicate whether the number is multiple of 3 or 5, respectively.
So, here's my truth_table... and... my design does not fit on the chip (compiler says)! How can i rework this if compiler isn't able to optimize it?

thanks much as always.

EDIT: i should say that i used GAL16V8D, is it possible to use this PLD or do i need to use something like GAL22?

Here's a hint -- look at the equations that the compiler generated, and think about how you can get the logic to fit if you generate an intermediate term and feed it back into the PLD as another input. It may take two passes through the small PLD to get the result. So it may take two or more clock cycles for the logic to propagate from new input data to valid output data.

 

[EvLer]

don't mean to overwhelm my post, but here are the equations generated by abel (i fit it on GAL22 for now)... could i have a hint

M3 = (N4 & !N3 & N2 & !N1 & N0
# N4 & N3 & !N2 & !N1 & !N0
# !N4 & N3 & N2 & !N1 & !N0
# N4 & !N3 & !N2 & N1 & !N0
# !N4 & !N3 & N2 & N1 & !N0
# !N4 & N3 & !N2 & !N1 & N0
# !N4 & !N3 & !N2 & N1 & N0
# N4 & N3 & N2 & N1 & !N0
# N4 & N3 & !N2 & N1 & N0
# !N4 & N3 & N2 & N1 & N0);

M5 = (N4 & !N3 & N2 & !N1 & !N0
# !N4 & N3 & !N2 & N1 & !N0
# N4 & N3 & !N2 & !N1 & N0
# !N4 & !N3 & N2 & !N1 & N0
# N4 & N3 & N2 & N1 & !N0
# !N4 & N3 & N2 & N1 & N0);

edit: i assume for GAL16V8 i need to "minimize" sum terms, of which there are 16 (OR-gates and 8 AND gates), right? well...i have 16!

 

[berkeman]

Those aren't the reduced equations, are they?

Edit/Hint -- Those are the "reduced" equations for positive logic, but check out the K-map for the inverted form. Try enabling the inverted form in your compiler. Does it not generate them also by default? Whenever your K-map has isolated 1's like that and big groups of 0's, the inverted equations will probably be more efficient.

 

[EvLer]

thanks! i reversed polarity and i think it fit...