Recent content by elektro2021

  1. elektro2021

    Engineering Simulating this cascoded NMOS logic circuit

    I don't know...I think that NMOS current depends by W/L...please help me
  2. elektro2021

    Engineering Simulating this cascoded NMOS logic circuit

    I think that Ic=C*(dv/dt) con C=100 fF and dv/dt= (VDD/2)/T con T=100ps and VDD=2.5V...what do you think?
  3. elektro2021

    Engineering Simulating this cascoded NMOS logic circuit

    Any help?
  4. elektro2021

    Engineering Simulating this cascoded NMOS logic circuit

    I think that I need to compute current charge/discharge for 100 fF capacitor...what do you think?
  5. elektro2021

    Engineering Simulating this cascoded NMOS logic circuit

    I think it's a XOR port for Y and XNOR for Y negate.I don't want to simulate the circuit by a simulator but I want to size (by hand) W/L for NMOS transistors to get a 100 ps delay (50-50) using 0.25 μm devices, while driving a 100 fF load on both differential outputs.
  6. elektro2021

    Engineering Simulating this cascoded NMOS logic circuit

    I need help for following exercise from Rabaey - Digital Integrated Circuits: A Design Perspective Size and simulate the circuit (IMAGE BELOW) so that it achieves a 100 ps delay (50-50) using 0.25 μm devices, while driving a 100 fF load on both differential outputs. (VDD = 2.5V) Assume A, B and...