Recent content by SpaceCreature

  1. S

    How Do Delays in Inputs Affect S-R Latch Outputs?

    I have a question about S-R latch for a specific diagram below (no, this is NOT a homework question). Is there something, physically, about the way that AND (or even other) gates are built that once they know one input, they know what the output will be? I know, for example, that if R = 0...