How Do Delays in Inputs Affect S-R Latch Outputs?

[SpaceCreature]

I have a question about S-R latch for a specific diagram below (no, this is NOT a homework question).

Is there something, physically, about the way that AND (or even other) gates are built that once they know one input, they know what the output will be? I know, for example, that if R = 0, the output of AND will be 0, because both inputs need to be 1 or high for the output to be 1. I'm guessing the answer is no, the circuit does not know what the output will be with one input because if R = 1, how do we know what the second input will be?

What boggles my mind is this: let's pretend that R always gives its output first, because for some reason there is a delay in S. How is this possible? How can there even be an output for either AND gate if the AND gate needs two inputs to make a decision about an output?

http://img839.imageshack.us/img839/3791/latchq.jpg

 

[Ratch]

SpaceCreature,

Is there something, physically, about the way that AND (or even other) gates are built that once they know one input, they know what the output will be?

2-input AND gates have 4 states; 00, 01, 01, 11 period. It bases its output solely on those states. The AND gate neither "knows" nor does it have any cognizance of what the next state will be. It operates on what is applied to the input at the current time.

What boggles my mind is this: let's pretend that R always gives its output first, because for some reason there is a delay in S. How is this possible? How can there even be an output for either AND gate if the AND gate needs two inputs to make a decision about an output?

What is the problem? The 2-inputs are going to be either 1 or 0. The AND gate will base its output on those current inputs.

Ratch

 

[LawRooney]

A high output simply means a current is flowing through the wires. If the S gate is slower than the R gate, than the R gate will be receiving a low signal from one of its outputs, and will produce a 0.

 

[NascentOxygen]

In a logic gates arrangement, at least those you will be working with, the signal at every point and on every wire is at all times either a 1 or else it's a 0, there are never any "undecided" or "still thinking about it" or "wait, I'm not ready yet" logic levels.

If a 2-input AND gate on one input has a 0, neither you nor the gate needs to take into consideration what is on the other input—the output of that AND gate is already determined to be 0 so the electronics is designed to make the output a 0.

 

[alphysicist]

Hello,

Thank you for your question about the S-R latch and its functionality. I can provide some insight into how AND gates work and how they contribute to the overall operation of the S-R latch.

Firstly, it is important to understand that AND gates, along with other logic gates, are electronic components that are designed to perform specific logical operations based on their inputs. In the case of an AND gate, the output will only be high (1) if both of its inputs are high (1). This is due to the physical construction of the gate, which utilizes transistors and other components to create a circuit that can perform this logical operation.

In the specific diagram you provided, the S-R latch utilizes two AND gates to control the state of its outputs. One AND gate is responsible for the R input, while the other is responsible for the S input. When R = 0, the output of the R AND gate will always be 0, as you correctly stated. However, this does not mean that the output of the S-R latch will always be 0. The other AND gate, which is controlled by the S input, may still have an output of 1, depending on the state of the S input.

In the scenario you mentioned where R always gives its output first, it is important to note that electronic circuits operate at very high speeds, often in the nanosecond range. This means that the delay in the S input would be extremely small and would not significantly affect the overall operation of the latch. Additionally, the output of the S input could still be determined by the other AND gate, even if there is a slight delay in its input.

In summary, the physical construction of AND gates allows them to determine their output based on the state of their inputs, regardless of whether they have one or two inputs. In the case of the S-R latch, both AND gates work together to control the state of the outputs, and any delays in inputs would be negligible due to the high speed of electronic circuits. I hope this helps to clarify your understanding of the S-R latch. If you have any further questions, please don't hesitate to ask.