yefj's latest activity
-
Yyefj replied to the thread s-parameter mathematical theory for crosstalk analysis.UPDATE: Hello , I have found the defintion of ICN as shown below in photo and attached document. The first one is integrated cross talk...
-
Yyefj replied to the thread s-parameter mathematical theory for crosstalk analysis.Hello berkerman, power sum Next is defined as shown below by the attached article. is there some mathematical expression for these...
-
Yyefj replied to the thread s-parameter mathematical theory for crosstalk analysis.Hello , I did google too before posting they dont show exact matematical manual to derive it. Is there some recoomended manual I could use?
-
Yyefj posted the thread s-parameter mathematical theory for crosstalk analysis in Electrical Engineering.Hello, I have a system shown in the photo .I have S-parameters of this system there are several tests like 1.integrated crosstalk noise...
-
Yyefj replied to the thread Design example for commercial high speed pcb.Hello , The basic Idea looks like the photo shown below. basickaly its a signal transition that accurs at very high digital signal...
-
YHello ,Is there a PCB example which is routing differential signal over many layers.where there could be many differential ports in...
-
Yyefj replied to the thread Inductive load contradicting short circuit load.Hello Baluncore,I also assume that our short circuit VIA can be represented as LC structure and also cause a problem as shown below...
-
Yyefj replied to the thread Inductive load contradicting short circuit load.Hello Baluncore,Gibbs effect if I understand correctly is saying that when our bandwidth is limited in the transmission line then...
-
Yyefj reacted to Baluncore's post in the thread Inductive load contradicting short circuit load with
Like.
Your via is an inductor, but if you have not trimmed the track where the via is located, it makes a small parallel plate capacitor in... -
Yyefj replied to the thread Inductive load contradicting short circuit load.Hello Baluncore, Sorry yes I understand. As you can see I simplified the model into one microstrip line with short at the end . From the...
-
YHello , As you can see in the simulation when we have a short load we have 0 impedance in the end because its 0 ohms. On the other hand...
-
YHello, I have built and simulated in CST a microstrip line with two discontinuetues. looking form port 1 we have one discontinuety at...
-
Yyefj reacted to Baluncore's post in the thread Time domain aliasing in VNA TDR measurement with
Like.
Yes. The conversion from the S-parameter sweep to time, assumes the step occurs at time = 0. If the data canot fit such an assumption... -
Yyefj replied to the thread Time domain aliasing in VNA TDR measurement.Hello Baluncore, suppose in VNA we have -50ns to 50ns. I understand that if we have signal in 0 to -50ns negative area is called...
-
Yyefj replied to the thread Time domain aliasing in VNA TDR measurement.Update: so given velocity factor 77% and cable length of 0.3m given the calculation in the photo we have round trip at 2.3ns. so given...
























