Space Qualified Level Shifter Solutions for 1.5V I/O to 1.8V I/O?

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SUMMARY

The discussion focuses on finding space-qualified level shifter solutions for interfacing a Xilinx Versal FPGA (P/N XCVC1902–1MSIVSVA2197) operating at 1.5V with a TI RF Sampler AFE (P/N AFE7950) that operates at 1.8V. The user seeks bi-directional I/O capabilities and mentions a part from ST Microelectronics (P/N 5962F1120701VXC) but finds it insufficient for 1.5V operation. Passive voltage dividers and BJTs are considered but are noted to be primarily unidirectional. The need for reliable voltage translation in high-reliability applications is emphasized.

PREREQUISITES
  • Understanding of FPGA I/O configurations, specifically Xilinx Versal architecture.
  • Knowledge of voltage translation techniques, including level shifters and passive dividers.
  • Familiarity with radiation-hardened components and their specifications.
  • Experience with interfacing ADCs, particularly the TI RF Sampler AFE (P/N AFE7950).
NEXT STEPS
  • Research space-qualified level shifters compatible with 1.5V to 1.8V translation.
  • Investigate the specifications and compatibility of the ST Microelectronics part (P/N 5962F1120701VXC) for 1.5V applications.
  • Explore datasheets for the Xilinx Versal FPGA and TI AFE7950 to understand their I/O requirements.
  • Learn about bi-directional level shifting techniques and components suitable for high-reliability applications.
USEFUL FOR

Engineers and designers working on high-reliability applications, particularly those involved in FPGA and ADC interfacing, as well as professionals seeking solutions for voltage translation in space-qualified environments.

ashah99
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TL;DR
In need of solutions for voltage translation between 1.5V I/O from FPGA to an ADC that accepts I/O at 1.8V
Hello everyone, I am trying to find level shifter/voltage translation solutions that are space-qualified (ideally radiation hardened, etc.) that can logic level translate from FPGA I/O at 1.5V to and ADC at 1.8V while supporting uni- or bi-directional I/O and OE capabilities . This is for high reliability applications. Basically, I am interfacing with SPI and some status/control discretes from the FPGA and the transceivers I/O are at higher voltages. I've found a part from ST Microelectronics (P/N 5962F1120701VXC) but the voltage isn't quite support and there's insufficient data at 1.5V. I also thought about passive voltage dividers or BJTs for translation, but those are mostly unidirectional.

Does anyone have good solutions that come to mind ? I appreciate any feedback/suggestions! Thank you.
 
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ashah99 said:
FPGA I/O at 1.5V to and ADC at 1.8V
Wow, interesting project. Can you post links to those two datasheets? It's hard to believe that the 1.5V part is not 1.8V tolerant, and even harder to believe that Vih and Vil of the 1.8V part are not compatible with the lower voltage CMOS outputs. Thanks.
 
berkeman said:
Wow, interesting project. Can you post links to those two datasheets? It's hard to believe that the 1.5V part is not 1.8V tolerant, and even harder to believe that Vih and Vil of the 1.8V part are not compatible with the lower voltage CMOS outputs. Thanks.
Sure, the FPGA selected is the Xilinx Versal (P/N XCVC1902–1MSIVSVA2197) and the other device is a TI RF Sampler AFE (P/N AFE7950). The plan is to use I/O from the XPIO bank from the FPGA to interface with the AFE. I have some datasheets referenced below, if you are interested.

https://www.ti.com/lit/ds/symlink/a...=https%3A%2F%2Fwww.ti.com%2Fproduct%2FAFE7950
 

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