# Can someone explain the operation of this NAND TTL

by FOIWATER
Tags: explain, nand, operation
 PF Patron P: 292 If some one could explain the operation of both the double emitter transistor and the circuit in general I would be very thankful. All the best, Attached Thumbnails
Mentor
P: 37,655
 Quote by FOIWATER If some one could explain the operation of both the double emitter transistor and the circuit in general I would be very thankful. All the best,
If either the A or B input is low, what do you think happens with Q1? And what does that cause to happen in the next stage...?
 PF Patron P: 292 I have been taught the classical "two diode" way of analyzing this type of circuit. If either A or B is low, transistor Q2 will not receive the required Vbe threshold voltage to conduct, let alone saturate. By the same logic, Q3 will not receive adequate voltage to conduct through it's junction.. Q4 conducts since its base is directly tied to Vcc, and the output is high. This logic is true whenever at least one input is low. But if both are high or floating, Q1 causes Q2 to saturate, voltage drop across R2 is adequate enough for Q3 to conduct, providing a path to ground for the signal, meaning output is low. Which corresponds to a NAND table, only low output is if both inputs are high. But I have recently been told by my circuit design teacher not to think of transistors in this "two diode" manner, so I was fishing for some real insight. Thanks for any additional information
HW Helper
P: 4,192

## Can someone explain the operation of this NAND TTL

 If either A or B is low, transistor Q2 will not receive the required Vbe threshold voltage to conduct
You skipped over what I would consider to be the most important feature and deserving a sentence or two, the way the unconventional Q1 controls Q2.
 PF Patron P: 292 Yes I don't understand it.
 PF Patron P: 292 It seems as though the way it operates is that if either one of the emitters of Q1 is attached to a low, Q1 will saturate.
HW Helper
P: 4,192
 Quote by FOIWATER It seems as though the way it operates is that if either one of the emitters of Q1 is attached to a low, Q1 will saturate.
OK, and this will in turn ....

Then the other case:
If A and B are both high? ......

BTW, homework questions should be posted in the homework forum.
 PF Patron P: 292 I explained it above --> what I think will occur in all these scenarios. If either input is low, Q1 will not saturate. The output is high If both inputs are low, Q1 will saturate, drive the base of Q2, which in turn saturates Q3, providing a path to ground for Vcc leaving the output low. But I have been told by my professor not to assume this "two-diode" method of analyzing these circuits (in a lecture, not by way of this specific example) Although I am a student and my course work has inspired the question, as it is not part of the curriculum, I did not deem it as homework. Just as a general question.
HW Helper
P: 4,192
 Quote by FOIWATER I explained it above --> what I think will occur in all these scenarios. If either input is low, Q1 will not saturate. ✗
 But I have been told by my professor not to assume this "two-diode" method of analyzing these circuits (in a lecture, not by way of this specific example)
I'd say the "two diode" model is perfectly acceptable for Q1. Give it a try.

Can you state the voltage that is needed on the base of Q2 for Q2 to adequately drive Q3?
 PF Patron P: 292 OK - so in using the two diode model - if either of the inputs is low - current is "steered" through one of the two diodes "pointing" to the left, so Q1 emitter does not drive Q2. What precisely was incorrect about the statement I made about saturation? I am not sure what voltage is required at the base of Q2, no
 P: 660 The logic function results perfrectly from a two-diode approach. So much so, that LS-TTL and ALS-TTL do use Schottky diodes instead of multi-emitter transistors. When having no fabrication process with Schottky junctions, the multi-emitter design had some advantages for the desaturation time, which didn't limit the input's speed, and for the area used by a many-input Nand. Who cares. What I really don't grasp: TTL and bipolar logic is as dead as a rat. Why do teacher keep telling about it decade after decade?
HW Helper
P: 4,192
 Quote by FOIWATER OK - so in using the two diode model - if either of the inputs is low - current is "steered" through one of the two diodes "pointing" to the left, so Q1 emitter does not drive Q2.
True. But it's the collector of Q1 that is connected to Q2, so you need to involve Q1 collector in your explanation.
 What precisely was incorrect about the statement I made about saturation?
How do you send a transistor into saturation? How would you recognize that a transistor is in saturation? What is a tell-tale characteristic of a transistor being in saturation?
 I am not sure what voltage is required at the base of Q2, no
Do these arrows give a hint?
Attached Thumbnails

HW Helper
P: 4,192
 Quote by Enthalpy What I really don't grasp: TTL and bipolar logic is as dead as a rat.
Didn't you say the same about CMOS? So if someone wanted to solder together a simple logic arrangement for the home or car, what technology do you say he should use?
 Why do teacher keep telling about it decade after decade?
The medium is the message.©
 PF Patron P: 292 The voltage required is Vbe(sat)? I thought you meant a specific voltage value, of that I would not know.. I am not sure how I would involve the collector of Q1 into it - but I do see what you mean.. Send a transistor into saturation by exceeding it's Vbe(sat), because increasing Vbe to a higher level increase base current, this increase in base current increases collector current, this increased collector current causes more of the voltage Vcc to be dropped across the resistor (say R3 for Q2) which leaves the Vce lower overall. Because this voltage is lower, the collector current becomes lower, which in turn causes Vce to increase, which in turn causes the collector current to increase and so on and so fourth. In terms of the energy band gap model I have been shown, this corresponds to the base to collector PN junction not having a depletion region, which prevents electron diffusion from ocuring and prevents current flow, so the addition of base current won't actually amplify the collector current, the electrons build up in a "cloud" in the base. At least this is what I have come to understand. So I guess the telltale sign of saturation is that the transistor effect doesn't apply after Vbe(sat).........?
HW Helper
P: 4,192
 Quote by FOIWATER The voltage required is Vbe(sat)? I thought you meant a specific voltage value, of that I would not know..
For any small signal silicon transistor, VBE is approx 0.6V while the transistor is functioning as a transistor. That's the voltage of a forward-biased PN junction. If you follow the arrows, to get from the base of Q2 to ground you must drop down two PN junction drops: VBE of Q2 then VBE of Q3. With each of these drops being approx 0.6V, it makes the base of Q2 how many volts?
 Send a transistor into saturation by exceeding it's Vbe(sat), because increasing Vbe to a higher level increase base current, this increase in base current increases collector current, this increased collector current causes more of the voltage Vcc to be dropped across the resistor (say R3 for Q2) which leaves the Vce lower overall. Because this voltage is lower, the collector current becomes lower, which in turn causes Vce to increase, which in turn causes the collector current to increase and so on and so fourth.
I don't think anyone speaks of Vbe(sat) of a transistor. It isn't a useful data figure, apart from being around 0.6 to 0.8V for every small signal transistor, and it varies with collector current so it's value conveys nothing useful.

Can you make use of google to better answer that question?
 PF Patron P: 292 OK I understand - Nascent, thankyou

 Related Discussions Career Guidance 2 Engineering, Comp Sci, & Technology Homework 4 Electrical Engineering 3 Engineering, Comp Sci, & Technology Homework 1 Electrical Engineering 1