Recent content by charkins

  1. C

    Self Bias Transistor Design Problem

    Homework Statement I have to solve for RD, RS1, and RS2. Homework Equations AVNL=-mg(Rd//rd) Vdd-Id(Rd+RStotal)=0 Bias Line Eq: Vg-Vgsq-Idq(RStotal) The Attempt at a Solution I have solved for RD by using the AVNL equation and the given value of -8 for AVNL. I found RD to be...
  2. C

    Common-Source JFET Amplifier problem

    Homework Statement For the prelab assume that the JFET has the following typical specifications: IDSS = 10.0 mA VGS(OFF) = -3.5 V rds = 50.0 kW 1. Complete the design for the bias circuit in Figure 1 given that the desired Q-point for the JFET is ID = 2.0 mA and VDS = 6.0 V by following these...
  3. C

    Single Stage Common Emitter Amp Design

    http://tinypic.com/view.php?pic=2ew1t0l&s=6 I believe this is how the circuit should be constructed I just cannot figure out how to solve for the missing values with the given parameters.
  4. C

    Single Stage Common Emitter Amp Design

    Homework Statement I am designing a voltage divider common emitter amplifier given the following parameters Av= 40 dB +/- 1dB Zi> 1000 ohms Zout< 5000 ohms Stability factor = 5 Beta*re= 650 ohms Beta minimum = 35 Beta maximum = 300 Vcc = 20 volts Rload = 33 kilo-ohms Rsource =...