Common-Source JFET Amplifier problem

[charkins]

Homework Statement

For the prelab assume that the JFET has the following typical specifications:
IDSS = 10.0 mA
VGS(OFF) = -3.5 V
rds = 50.0 kW
1. Complete the design for the bias circuit in Figure 1 given that the desired Q-point for the
JFET is ID = 2.0 mA and VDS = 6.0 V by following these steps:
(a) Calculate the following values for this JFET:
VGS = _____________ gm = _____________

Homework Equations

gm = 2 * Id / Vgs - Vth

The Attempt at a Solution

Is it safe to assume that VGS(off) is the pinch off voltage for the transfer plot?
What is rds?

 

[NascentOxygen]

rds = 50.0 kW

r_ds is the ON resistance from Drain to Source, i.e., when V_GS=0, the JFETS's miminum* resistance. Typically 10s to 100s of Ohms for ordinary JFETs. r_ds has units of Ω, not kW. You may include r_ds when determining the slope of the load line.

A handy JFET reference: http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-101-introductory-analog-electronics-laboratory-spring-2007/study-materials/jfet.pdf[/color]

 

[aralbrec]

r_ds is the ON resistance from Drain to Source, i.e., when V_GS=0, the JFETS's miminum* resistance. Typically 10s to 100s of Ohms for ordinary JFETs. r_ds has units of Ω, not kW. You may include r_ds when determining the slope of the load line.

A transistor amplifier is operated in saturation, so rds wil not be involved in any load line. It may, however, help to determine some unknown transistor parameter. As mentioned, rds is the approximate resistance between the drain and source when the transistor is in triode with vds small.

Edit: And yes, that will be the pinch off voltage.

 

[NascentOxygen]

Data sheet for your 2N3819: http://www.datasheetcatalog.org/datasheet/vishay/70238.pdf[/color]