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Common-Source JFET Amplifier problem

  1. Nov 6, 2012 #1
    1. The problem statement, all variables and given/known data
    For the prelab assume that the JFET has the following typical specifications:
    IDSS = 10.0 mA
    VGS(OFF) = -3.5 V
    rds = 50.0 kW
    1. Complete the design for the bias circuit in Figure 1 given that the desired Q-point for the
    JFET is ID = 2.0 mA and VDS = 6.0 V by following these steps:
    (a) Calculate the following values for this JFET:
    VGS = _____________ gm = _____________


    2. Relevant equations

    gm = 2 * Id / Vgs - Vth

    3. The attempt at a solution

    Is it safe to assume that VGS(off) is the pinch off voltage for the transfer plot?
    What is rds?
  2. jcsd
  3. Nov 7, 2012 #2


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  4. Nov 8, 2012 #3
    A transistor amplifier is operated in saturation, so rds wil not be involved in any load line. It may, however, help to determine some unknown transistor parameter. As mentioned, rds is the approximate resistance between the drain and source when the transistor is in triode with vds small.

    Edit: And yes, that will be the pinch off voltage.
    Last edited: Nov 8, 2012
  5. Nov 8, 2012 #4


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