I Cant Understand this mux implementation

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The discussion centers on the implementation of an 8-to-1 multiplexer (MUX) using 2^3X4 and 2^3X1 programmable read-only memories (PROMs), specifically addressing the complexity introduced by a chip select input. The user expresses difficulty in understanding the circuit and programming tables provided, particularly how the select lines (s0, s1, s2) interact with the PROMs. Despite tracing the circuit manually, the user struggles to grasp the logic behind the output patterns compared to a standard MUX configuration. Additional links to circuit diagrams and programming tables are shared for clarity. The conversation highlights the challenges of interpreting complex digital circuit designs.
transgalactic
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i need to implement a 8-1 MUX using 2^3X4 and 2^3X1 proms

where there is a chip select input in the MUX

here is the solution of the circuit and the programming tables


http://s290.photobucket.com/albums/ll279/t...=IMG_8816-1.jpg

i can't understand this circuit
there is s0 that goes in every prom independently
there is a chip select input inside of the "main prom"

i tried to trace out the way it works with pencil and paper
but this this really tough to understand

i couldn't get this pattern like in ordinary mux
that if we take s0=0 s1=0 s2=1 then take I1
eventually i got to the right answers
but i coudnt understand why?
 
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Hi Galactic, where is the ckt n prog table? instead i watch some ... :-(
 
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