I'm not familiar with the Motorola 68k series, so I need to ask how many address and data lines does it provide? You need to draw out a memory map with the 24 memory chips mentioned in the question plus the memory-mapped IO. The EEPROM will most likely be at the bottom of the memory map (starting at 0x000000), since the 68k will need some non-volatile memory to run its boot program from, and I'd guess the 68k starts executing at 0x000000 after reset (is this right?).
So the 8 EEPROM chips take up the first 4MB of the memory map, from 0x0000 to 0x3FFFFF (divided into the 8 half-MB chunks), the 8 SRAM chips would go next, from 0x400000 to 0x4FFFFF, and so on. The last 128 bytes at the top after the DRAM chips are memory-mapped IO.
Now you need to look at the memory control lines for each type of memory, and design a circuit that takes in the address lines and the control lines from the 68k (like R/W- or whatever), and generates the enable lines for the different memory chips (like OE-, CS-, etc.). For example, when your decode circuit sees the address 0x000000 and the appropriate control lines from the 68k, it will generate a CS- for the bottom EEPROM chip (and *only* that chip), along with an OE- if it is a read cycle, or a WE- if it is a write cycle.
You typically would implement this kind of memory decode circuit in a CPLD or an FPGA. You can use Verilog or ABLE or whatever to code up the CPLD/FPGA. How are you asked to code up and simulate/test this design?