SRAM randomization?

[Artlav]

Hello.

While tinkering with some digital circuits i noticed a peculiarity i don't quite understand.

The culprit is an SRAM memory block, used as a video buffer (specifically, IS61LV25616 asynchronous CMOS static ram), which on power on remains in it's uninitialized state.

As could be expected, the image appears to be quite random.

However, there is a peculiarity - the random is not very random.
If i compare the content between two power cycles without writing anything, there would be only about 1-2% of difference.
If i write something into it, then cycle the power, it is no more than 10-20% different from the baseline.
The baseline is writing all 1's, then turning off for 10 seconds.

More interestingly, if i write something into it, power cycle, write something else, power cycle, write the first thing again, power cycle, then the decays of first and third ones would still be only about 1-2% different, and 1 and 2 could be anything between 2 and about 20% different.

It appears that there is some kind of default pattern it settles into when unpowered, slightly altered by it's prior content.

I wonder what is causing it?
Where are the origins of that pattern?


Another thing along the same alley - the SRAM is often noted for it's high data remanence, however turning the power off even for a fraction of a second (in human terms) results in a completely randomized image.
What have i missed there?

[phyzguy]

Ideally an SRAM cell is perfectly symmetric and is equally likely to be found in either state. However, in practice the transistors forming the SRAM have statistical variations in their parameters (such as threshold voltage and transconductance) which give each cell a preferred state. On power-up, each SRAM cell will settle into its preferred state. This is why the state of the SRAM array on power-up is not random, but appears to have a pattern. You need to write the cell in order to get it into a known state.

[Artlav]

Makes sense, thank you.

What about the data remanence?