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Turning JKFF flip-flop into DFF |
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| Mar25-12, 01:14 AM | #1 |
| Mar25-12, 04:50 AM | #2 |
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If you attach not gate to K (from J input) only 2nd and 3rd lines from JKFF truth table will be possible states. Thus your DFF will work as expected.
BTW, the 1st line of JKFF is wrong. It will be 0 0 Q Q' The 1st and 2nd lines of DFF will be 0 0 Q Q' and 0 1 Q Q' |
| Mar25-12, 06:30 AM | #3 |
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Start with your input CLK and D and fill it in. Then 2 columns for J and K. Leave them empty for now. And then a column for the expected output Q and fill that in too. Now how do you need to fill in the columns for J and K to get the output Q? If you have that, you can make a logic circuit to get J from CLK and D, and also one to get K from CLK and D. ![]() It won't help you here though.
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| Mar25-12, 06:39 AM | #4 |
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Turning JKFF flip-flop into DFF
If I may interrupt... With the given truth tables the discussion would be right. But maybe the D-FF is supposed to be edge-triggered, and it is precisely the edge-triggering logic that the OP is being asked to implement. Maybe.
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| Mar25-12, 03:50 PM | #5 |
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I didn't really think about that. Still, I think the method will still work if we interpret each value for CLK in the table as being different from the one before. |
| Mar25-12, 07:12 PM | #6 |
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The JK flip flop is a clocked device. Look up the 7476 for example. The problem is a lot easier if you assume this.
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| Mar30-12, 11:25 PM | #7 |
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| Mar31-12, 08:12 AM | #8 |
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| Mar31-12, 11:15 AM | #9 |
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00 and 11
so 00 = No change 11 = Flips values Same as DFF |
| Mar31-12, 11:18 AM | #10 |
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So this is not the solution to your problem. |
| Mar31-12, 11:23 AM | #11 |
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Are you telling me my teacher was wrong?
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| Mar31-12, 11:27 AM | #12 |
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Apparently he told you to connect the J and K inputs, which is something you can do. However, it does not generally turn JFKK into DFF. You need more to do something like that. |
| Mar31-12, 11:43 AM | #13 |
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I just looked up JK flipflop and realized that it has a 3rd input: the clock pulse.
Both JF and D flipflops only change state on a clock pulse trigger. It means you can ignore the clock pulse trigger and look only at the D-input. You need to turn the D-input into J and F inputs. So you need a truth table with only D-input, show intermediary J and K inputs, and end up with a Q-output. It means a slight tweak to the solution your teacher gave you. |
| Mar31-12, 11:59 AM | #14 |
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ILS -- can you confirm this?
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| Mar31-12, 12:06 PM | #15 |
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What Kholdstare says is the same as what you already have. I think he misinterpreted the NC entries. For instance, he meant that the 1st line of JFKK should be ##0\ 0\ Q\ \overline{Q}##. But this is the same as ##0\ 0\ NC\ NC##. That is, you get a D-input, try to connect it to a JKFF somehow, and try to get the related DFF output. Did you mean it differently? |
| Mar31-12, 12:08 PM | #16 |
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the value of clk doesn't generally get included in a truth table, because the operation of a clocked flip flop is not dependent on its value, rather on its edge. a truth table for a clocked device is generally supposed to be interpreted as "what happens when you get a triggering edge on clk"
![]() ![]() those two images are easier to work from, and you can see that the D output matches the jk output for two specific cases, D = 1 matches J = 1,K = 0, and D = 0 matches J = 0, K = 1. with that information, can you see the combinational logic circuit required to take D as input, and J, K as output? edit: just noticed that clk is included in the t-tables i posted, despite me saying that they shouldn't be there. all that entry is showing is that this is only valid for a rising edge on clk, and since they all have it, the conclusion is that without a rising edge nothing happens... |
| Mar31-12, 12:53 PM | #17 |
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