BCD to 7 segment display logic minimisation

  • Thread starter fonz
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In summary: Your 3rd minterm does include A', and I get the same minterms as you now. I have attached the corrected K-map and grouped the terms according to the minterm you are missing.I have attached the corrected K-map and grouped the terms according to the minterm you are missing.In summary, the 7-segment display is used to show a decimal digit and it is driven from 4-bit input. Each bar is assumed to light up when a logical 1 is applied to it. Draw the truth table to drive segment (d) of the display. Using the truth table you have obtained, draw a Karnaugh map to find the minimised logic expression
  • #1
fonz
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Homework Statement



A 7-segment display is used to show a decimal digit and it is driven from 4-bit input. Each bar is assumed to light up when a logical 1 is applied to it.
  1. Draw the truth table to drive segment (d) of the display.
  2. Using the truth table you have obtained, draw a Karnaugh map to find the minimised logic expression in the 1-st canonical form (SOP, i.e. series of AND terms ORed together).
  3. Convert the expression from 2 to a function which uses only NAND gates and draw the equivalent circuit diagram in Logic Circuit and generate its truth table to compare with 1.
seven-segment_example.png

Homework Equations



De-Morgan's laws:$$(A + B)' = A' \cdot B'$$$$A' + B' = (A \cdot B)'$$

The Attempt at a Solution


[/B]
See attached for truth table and k-map.

Canonical Form:$$A + C'D + CD' + A'B'$$

Applying De-Morgan's Theorem:$$A'BCC'DD'$$

but since ##C \cdot C' = 0## and ##D \cdot D' = 0## then this all reduces to 0.

I'm not sure whether it is my K-Map minimisation or application of De-Morgan's laws that is wrong?
 

Attachments

  • segment_d.png
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  • #3
Yes that is correct thanks berkeman.
 
  • #4
fonz said:
used to show a decimal digit
And this part of the problem statement implies you should only show 0-9 and blank on any number 10 and up? Or are you supposed to display A-F too...
 
  • #5
berkeman said:
And this part of the problem statement implies you should only show 0-9 and blank on any number 10 and up? Or are you supposed to display A-F too...

In the example that was provided for segment c, the decimal values 10 to 15 are shown as 'don't care' terms so I have kept it consistent with the example.
 
  • #6
I'm confused though. You should end up with 7 truth tables, one for each segment drive, right?
 
  • #7
berkeman said:
I'm confused though. You should end up with 7 truth tables, one for each segment drive, right?

Yes in total, although this homework is only to derive the logic circuit for segment d.
 
  • #8
Ah, okay. I missed that if you said it in your OP. Let me check your work now...
 
  • #10
berkeman said:
d should not be 1 for the digit 9...

Well, I guess it could, but I normally wouldn't make d ON for 9.

I did think this originally but then I checked the example solution that was provided in the homework material and found this.
 

Attachments

  • segment.png
    segment.png
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  • #11
fonz said:
I did think this originally but then I checked the example solution that was provided in the homework material and found this.
Ah, fair enough. The issue I see is the blue rectangle and green rectangle that you have around 3 terms each in your K-map. I don't think you can do that... :smile:

http://www.ee.surrey.ac.uk/Projects/Labview/minimisation/graphics/g3.gif
g3.gif
 
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  • #12
Great thanks for pointing that out, still got the same issue though:

Canonical:

##A + BC'D + B'C + B'D' + CD'##

Applying De-Morgan's law:

##A'BBB'CC'C'DDD'##

Now the ##BB'##, ##CC'## and ##DD'## terms all equal zero.
 

Attachments

  • segment_d.png
    segment_d.png
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  • #13
fonz said:
A+BC′D+B′C+B′D′+CD′
That's not what I'm getting for a corrected version of your K-map. Can you post the corrected K-map and show your groupings?
 
  • #14
berkeman said:
That's not what I'm getting for a corrected version of your K-map. Can you post the corrected K-map and show your groupings?

I think I am missing the ##A'## from the third minterm.

##A + BC'D + A'B'C +B'D' + CD'##
 

Attachments

  • segment_d.png
    segment_d.png
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  • #15
fonz said:
I think I am missing the A' from the third minterm.

A+BC′D+A′B′C+B′D′+CD′
Your 3rd minterm does include A', and I get the same minterms as you now. :smile:
 

1. What is BCD to 7 segment display logic minimisation?

BCD stands for Binary Coded Decimal and is a way of representing numbers in binary form. A 7 segment display is a type of electronic display commonly used to display numerical characters. BCD to 7 segment display logic minimisation is the process of simplifying the logic circuitry needed to convert BCD numbers to the corresponding segments on a 7 segment display.

2. Why is logic minimisation important in BCD to 7 segment display?

Logic minimisation is important because it helps reduce the complexity and size of the logic circuitry needed for BCD to 7 segment display conversion. This leads to more efficient and cost-effective designs.

3. What is the difference between SOP and POS logic minimisation?

SOP (Sum of Products) and POS (Product of Sums) are two different methods of logic minimisation. SOP involves writing the output of a circuit as a sum of products, while POS involves writing the output as a product of sums. The main difference between the two is the arrangement of the inputs and outputs in the resulting logic expressions.

4. How do Karnaugh maps help with BCD to 7 segment display logic minimisation?

Karnaugh maps, also known as K-maps, are graphical tools used to simplify Boolean expressions. They are particularly useful for logic minimisation in BCD to 7 segment display as they allow for a visual representation of the truth table and help identify patterns in the input and output values.

5. What are some common optimization techniques used in BCD to 7 segment display logic minimisation?

Some common optimization techniques include using Karnaugh maps, applying Boolean algebra laws, and using don't care conditions to reduce the number of terms in the final logic expression. Other techniques such as using multiplexers and ROMs can also be used to further optimize the logic circuitry.

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