Recent content by j777

Nut inserts probably aren't what you'd want for your application but I thought they would be worth mentioning because they come in handy sometimes. For example, when a "backer plate" is desired in the bottom of an enclosure and you want to put standoffs on it to mount PCBs...

Let me rephrase and recap... Here's my stackup Here are the standard 6 layer spacings from the shop that makes the blank boards. I'm using a 3.3V supply for the MCU's IO and 1.8V supply for its core. I flooded layer 5 (PWR) with the 3.3V power plane because it is required all over the...

See the following sites for info http://en.wikipedia.org/wiki/Fpga" http://en.wikipedia.org/wiki/CPLD" http://www.opencores.org/" BTW you'll probably have more luck asking this question in the Electrical Engineering forum

Well I have one thing left to route on the board; the 1.8V power plane. I went with the 6 layer stackup and I have all the TLs on Sig1 and Sig2. I was planning on putting the 1.8V power plane on Sig3 under the MCU but some of the TLs run under the MCU. My concern is that the TLs that run under...

Thanks for all the input. I still don't know what the 100 Ohm resistor is for but my theory for the zero Ohm resistor is that it gives the user the option of accessing the SD card via SPI or SDIO. Does that make sense?

I'm not so sure that it's just a jumper... Here's a snippet from a similar eval board. In this schematic the resistor is R35. Any ideas? The full schematic for this snippet can be viewed is at http://www.olimex.com/dev/images/ARM/ATMEL/SAM9-L9260-REV-B-sch.gif"

I'm almost finished with it. Well at least my first attempt; I've never attempted a board as complex as this one so I wouldn't be surprised if I have to make some changes and build another prototype. Just in case anybody is interested I ended up going with a microSD connector because they...

I'm studying a portion of a schematic from an evaluation board. What's the purpose of R20 in the attached schematic?

Thanks berkeman. Better safe than sorry...I found a connector made by ALPS (their SCDA series) that has "standoffs" which space the connector off the board 1.8mm.

Hello, If vias are covered with soldermask is it OK to mount an SD card connector with a metal frame over the top of them? Thanks

I'm trying to figure out what's the best way to orient the two SDRAM chips. If I use the 4 layer stackup I should be able to get most of the address lines on the top layer OR get most of the data lines on the top layer. Which is it better to have on the top? Another key aspect of the decision...

Thanks for all the help. I'm going to take another look at my floorplan as you've suggested and see what I come up with. I think the only clocks that I have running around are the serial clock (SD/MMC card and DataFlash) and the system clock for the SDRAM; I may have to consider termination...

Thanks for the response berkeman. I found the following in the forum about forward and back termination. Please explain how this applies to my situation? In the 4 layer stack-up should I be worried about putting transmission lines in layer 3 since it is 39mils from layer 2 (GND)? It...

For the 4 layer stackup the spacings are Sig1->8.3mil->GND->39mil->Pwr/Sigs->8.3mil->Sig2. For the 6 layer stackup the spacings are Sig1->8.3mil->GND->14mil->Sig2->8.3mil->Sig3->14mil->Pwr->8.3mil->Sig4. This is the first design where I have to consider the Zo of the transmission lines...

Ok...so if I understand what your saying properly I can do the following: 1. Sig1 - Most transmission lines (I definitely can't fit them all on this layer) 2. GND - Ground plane 3. Pwr - Power and the rest of the transmission lines that I can't fit on Sig1 4. Sig2 - Low frequency stuff...