Recent content by shaikss

I have attached the circuit. Now, tell me what circuit can be added so that I can reconfigure the circuit either to 3-stage or 4-stage.

Hi, I had designed a rectifier with 4 stages. I want to design a re configurable circuit in such a way that I can use either 2-stage or 3-stage of the rectifier depending upon the output voltage. Output voltage depends on the distance between reader and tag. If both are near, then the output...

Part '3'...I have connected the drains to the gates. I believe the connection is missing in the figure. Yaa, what u said about the operation of ckt is right. But I don't understand whenever signal is there, output should be logic '1' and when no signal present, logic '0' should be at output. I...

Hi, I am designing an ASK demodulator for RFID Tags. I have attached the circuit diagram. This is the ckt from IEEE paper. If you look at the ckt, the first stage is the inverter kind of thing. I didn't get why second NMOS is used for Stage I. Similarly, the second stage is also inverter...

Hi Folks, I have designed a rectifier and a regulator as independent entities. Both of these blocks are working fine when simulated in virtuoso independently. But when I integrate them, i.e when I connect regulator to rectifier, I am unable to see regulated output. I have attached the...

Voltage is dropping down ! Hi Folks, I have designed a rectifier and regulator for RFID Tag. Both are working fine when they are simulated independently. When I gave 500mV as input to 4-stage rectifier, I got 1V output for open load ckt condition. Now, I have connected rectifier to...

Hi, I am designing a RFID rectifier. I am referring a IEEE paper for this purpose. The paper has shown results for both 130nm and 350nm technologies. I have chosen 180nm technology. So, I expected results in between the above technologies. To my surprise, the results are weird -...

I want to simulate the same in cadence for one of my module. For one of my modules, I need to design half pulse shaping circuit.The input is the digital data - logic 1 and logic 0. The output should be positive cycle of sine wave when logic 1 is present and negative cycle when logic 0 is present.

Hi, I need to design a circuit which gives positive half cycle of sine wave when logic 1 is given as input and negative cycle of sine wave when logic 0 is input. Please let me know how to design the same using cadence.

Hi, For any biomedical applications, the sensor output has to be amplified and digitized. For amplification, we use Instrumentation amplifier. But the output of IA has some dc voltage. So, how to suppress the dc voltage. At the same time, all biomedical signals are low frequency signals in...

Hi, Can you please let me the impact of current loading for the attached circuit? The attached circuit is a 4-stage dc-dc converter- charge pump. When I give an input voltage of 1V, the output voltage is around 4.6 V using cadence simulations. The expected output voltage is 5V. I am...

Hi, I am sending you the paper, where I got this circuit. Can you please check it out and let me know. Please help me out.

Homework Statement I want to find the overall transfer function of Instrumentation amplifier with a DC-Suppression filter. I know how to calculate the TF of a normal Instrumentation amplifier. But when feedback is given from the Filter to the IA, I couldn't find it. Homework Equations...

Hi, Can you please let me know how does the attached circuit work? Vh and Vl are inputs ; Vbn and Vbp are outputs. Thanks in advance.

I need your help in understanding the concept. Actually, I am trying to understand the grounding concept here: Attached is the snapshot: Hi Folks, I need your help in understanding the concept of how to measure the output voltage. 1. Initially, I tried to monitor the voltage...