Recent content by yefj
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s-parameter mathematical theory for crosstalk analysis
UPDATE: Hello , I have found the defintion of ICN as shown below in photo and attached document. The first one is integrated cross talk noise,my victim is line 1->2. Next is the coulping from near aggressor lines. S31 S51 S71 NL0 is the coupling from port 3 to 1 ,S31 NL1 is the coupling from...- yefj
- Post #6
- Forum: Electrical Engineering
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s-parameter mathematical theory for crosstalk analysis
Hello berkerman, power sum Next is defined as shown below by the attached article. is there some mathematical expression for these terms? 1.MDNEXT(multi distributed NEXT) 2.Normalized MDNEXT.- yefj
- Post #5
- Forum: Electrical Engineering
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s-parameter mathematical theory for crosstalk analysis
Hello , I did google too before posting they dont show exact matematical manual to derive it. Is there some recoomended manual I could use?- yefj
- Post #3
- Forum: Electrical Engineering
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s-parameter mathematical theory for crosstalk analysis
Hello, I have a system shown in the photo .I have S-parameters of this system there are several tests like 1.integrated crosstalk noise which uses victim S-params near end and far end cross talk 2.PSXT (power sum cross talk) 3.MDNEXT(multi distributed NEXT) 4.Normalized MDNEXT. Is there some...- yefj
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- Replies: 5
- Forum: Electrical Engineering
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Design example for commercial high speed pcb
Hello , The basic Idea looks like the photo shown below. basickaly its a signal transition that accurs at very high digital signal passing threw from top layer to the buttom layer and we have not one differential pair but 10 such pairs. Is there a manual or design example I could use to build...- yefj
- Post #4
- Forum: Electrical Engineering
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Design example for commercial high speed pcb
Hello ,Is there a PCB example which is routing differential signal over many layers.where there could be many differential ports in between then. Is there such real life example I could try to do EM simulation from it? Thanks.- yefj
- Thread
- Replies: 5
- Forum: Electrical Engineering
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Inductive load contradicting short circuit load
Hello Baluncore,I also assume that our short circuit VIA can be represented as LC structure and also cause a problem as shown below in the photo and attached LTspice simulation . Which can also create ringing in TDR.As shown in the photo 66ps ringing period is 15GHz which is very close to...- yefj
- Post #8
- Forum: Electrical Engineering
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Inductive load contradicting short circuit load
Hello Baluncore,Gibbs effect if I understand correctly is saying that when our bandwidth is limited in the transmission line then harmonic data gets filtered thus given us ripples(sinusoidal data). I have built the Ltspice simulation shown below and attached the LTspice file. few questions: 1...- yefj
- Post #6
- Forum: Electrical Engineering
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Inductive load contradicting short circuit load
Hello Baluncore, Sorry yes I understand. As you can see I simplified the model into one microstrip line with short at the end . From the power flow simulation the signal reaches the short at 0.44ns. few questions: 1.As you can see in the CST TDR when the signal comes back from the short at...- yefj
- Post #3
- Forum: Electrical Engineering
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Inductive load contradicting short circuit load
Hello , As you can see in the simulation when we have a short load we have 0 impedance in the end because its 0 ohms. On the other hand as you can see below in the simulation when we have inductive load then we have negative bump in the tdr. A shorting via can ve viewed as inductor because its...- yefj
- Thread
- Replies: 8
- Forum: Electrical Engineering
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Seeing microstrip geometry in the TDR plot
Hello, I have built and simulated in CST a microstrip line with two discontinuetues. looking form port 1 we have one discontinuety at 8.25mm the second one is at 36.25mm=8.25+10+18 given velicity factor 36mm and 8.25 mm roundtip where calculated at 740ps and 170ps. few questions: 1.could you...- yefj
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- Replies: 1
- Forum: Electrical Engineering
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Time domain aliasing in VNA TDR measurement
Hello Baluncore, suppose in VNA we have -50ns to 50ns. I understand that if we have signal in 0 to -50ns negative area is called casuality. That things happen before the input. If I understand correcly it could happen because of bad deembeding or bad sampling of the S-params, or bad rise time...- yefj
- Post #4
- Forum: Electrical Engineering
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Time domain aliasing in VNA TDR measurement
Update: so given velocity factor 77% and cable length of 0.3m given the calculation in the photo we have round trip at 2.3ns. so given my calculation is from -50ns to 50ns I will have the TDR pulse only on the positive side. The problem with this consept is if we have a system where we have...- yefj
- Post #2
- Forum: Electrical Engineering
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Time domain aliasing in VNA TDR measurement
Hello, alyasing by nyquist theorem where we have analog signal at some frequency and we sample it at some rate so we need the sample rate to be twice higher the the analog signal frequency. we set TDR in VNA from negative to positive -50ns to 50ns for example we have a circular 100s. Our signal...- yefj
- Thread
- Replies: 4
- Forum: Electrical Engineering
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Properly producing TDR on PNA network analyzer N5224B
Hello ,few questions regarding your good presentation: 1.reflection coefficient is shown in the formula, If we know Zo then if we know reflection coefficient then we know the reflection impedance of the TDR. How does the VNA know what is Zo (characteristic line impdance) 2.How Do I set in the...- yefj
- Post #17
- Forum: Electrical Engineering