Help with PIC Architecture: Timing Diagram & PC Values

[mathrocks]

I need some help with the PIC (PIC16F84) architecture. I am suppose to write timing diagram, including values of the PC (program counter), for the following instruction sequence when (a) the BTFSC (bit test register f, skip if set) instruction results in a skip and (b) when it does not.

Address Instruction
50 BTFSC
51 ADDLW
52 SUBLW


Does anyone know what this means? All I know is that I'm suppose to show when instructions are Fetched and Executed.

 

[NoTime]

Cycle counting is important if you are doing real time programing.
You need to know it the task can complete in the time allotted for it.

I'm not familiar with the PIC specifically, but you need to look in the processor handbook. It should give the clock cycle counts for the instruction + address mode data fetch clocks + branch clocks.

For example the BTFSC might take 5 clocks to fall thru or 10 clocks to branch.
The ADDLW might take 4 clocks for immediate data or 10 for pointer data.

You seem to have the right idea.

 

[TenaliRaman]

These should help you,
ww1.microchip.com/downloads/en/DeviceDoc/35007b.pdf
web.mit.edu/rec/datasheets/PIC16F84.pdf

-- AI