Decoding DDR Memory Organization: Understanding 1Gb DDR2 SDRAM Datasheet

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The 1Gb DDR2 SDRAM is structured in rows, columns, and banks, specifically as 64Mb*16 data lines, equating to 8Mb*8 banks with 16 data lines. The datasheet indicates 13 row address lines, leading to 8192 rows, and 8 column address lines, resulting in 256 columns, which collectively yield a configuration of 2Mb per bank. Each bank is organized as 8192 by 256 by 64 bits, with 10 column select bits, of which 8 are utilized for column selection. The discussion also raises a question about the necessity of precharging a row before selection, indicating a deeper inquiry into DDR memory operation. Understanding these details is crucial for effectively working with DDR memory technology.
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I was going through the datasheet of 1Gb DDR2 SDRAM. It's organized in rows, columns and banks.
The 1Gb is actually 64Mb*16 datalines.
Which is 8Mb*8 Banks * 16 data lines
I can't figure out how they got 8Mb?

In the datasheet block diagram (attached), there are 13 row address lines. So 2^13 = 8k
there are 8 column addr lines, so 2^8 = 256
8192*256 = 2Mb ?
 

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Hi likephysics. Each bank is actually organized as 8192 by 256 by 64 bits. There are 10 column select bits, but only 8 of them are used to actually select the column. The remaining 2 are used to select the correct 16 bit word from the 64 bit bank output.
 
uart, Thanks.
One more DDR question - why do you need to precharge a row before selecting it?
 

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