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Other How does research work, as far as facilities are concerned?

  1. Apr 11, 2017 #1
    I am an undergraduate electrical engineering student, and I have thus far in my collegiate experience lived in the library. I've learned a lot, and have written lots of embedded software and developed my own boards for various projects. I recently started designing my own ASIC (an application-specific chip) and want to make it. My university has its own fabrication facility for IC's, and some of my professors even do research in there. I was never able to do any "undergraduate research", but I want to know how I might be able to get trained on the machinery and make my chip. Money is no object, so I wouldn't need any kind of funding. I just want to know what the procedure is for using research facilities in general and if I would have to be a graduate student to use university equipment, especially if I'm not just an assistant but am doing my own thing (if thats even allowed).
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  3. Apr 12, 2017 #2


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    I think you should talk to those professors about your situation.
  4. Apr 12, 2017 #3


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    There is no way you will be able to use a cleanroom for free. Running and maintaining cleanroom equipment is expensive and most universities/institutes will have a system where the researchers either pay for time (time in the cleanroom and time using equipment) OR they pay a fixed percentage of any any research grant for projects that use the cleanroom in some way. The hourly fee for running more sophisticated pieces of kit (deposition systems and lithographers) can be quite high; and you also pay for the time it takes to pump down the chambers once a sample has been loaded (which is often several hours)

    For one of the cleanrooms we use have semi-commercial access (reduced rate); a typical run with a single layer film and one e-beam lithography step resulting in a single 2" wafer will be about £3000, and that is when we do ALL the work. Using photolithography is of course cheaper but then you still need at least one mask (about £300 or so).
  5. Apr 12, 2017 #4
    I was aware of the cost and was not expecting a "free lunch." But I can pay for the cleanroom fees and material costs up front, so I would not need to be involved in grants/funding. I'm just asking about permission to conduct activities in there. Thank you for the information.
  6. Apr 12, 2017 #5


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    How complicated is your design? If it is a single or possibly two layer design that can be made using photolithography I guess it is possible that they would allow you to use the tools if you can pay the fees. Note that your also need to include the cost of the training; it typically takes a PhD student about 3 months to learnt the basics (working 2-3 days/week in the cleanroom).

    Note also that if you are talking about a "proper" digital ASIC it is very unlikely that the cleanroom at your university can make one; academic cleanrooms are typically not set up for that kind of work. they tend to focus on making prototypes of single components. not large ICs (I am not aware of any academic cleanrooom that can do foundry-type work). ASICs are typically made in foundries that specialize in that type of fab The methods used are set up for mass production (the tooling costs are so high that it makes no sense to make individual chips) and a the cost of a production run of a "normal" ASIC is of the order of $500K or so.
  7. Apr 12, 2017 #6


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    It is time for you to get out of the library and talk to people, first hand, one-on-one.

    Approach one of your EE professor. Ask him/her if there is a way for you to use such facilities for whatever the reason. Unless he/she is the "owner" or manager of such a facility, that professor will be able to direct you to the person responsible.

    I do not see such permission granted for a personal project. There are legal liabilities involved here. If you get hurt, will the facility/school be responsible since you're there on your own free time? So there are issues involved here beyond just the cost of using the facility.

    But you need to get out and ask!

  8. Apr 12, 2017 #7
    In response to ZapperZ, I think what I'll do is get out of the library during the summer semester (no classes) and just try to find a place to be of use as an assistant in a lab. I don't have a job, friends, or coursework during the summer, so I'll be able to entirely focus on whatever I'm tasked with and spend a lot of time on my work. Thanks for the advice.

    I see what f95toli is saying. My ASIC is just a simple single layer affair (and not of incredibly practical use), but I've been daydreaming about something more complex that would be a development of the current one applicable to practical uses. You are correct about my university's cleanroom not being equipped to do anything more than research on single-layer component prototypes, and so I looked online at actual ASIC fab services such as MOSIS. I think I'll stick with daydreaming and just wait to win the lottery... :smile: Thanks for all of the information.
  9. Apr 12, 2017 #8
    This is why some researchers will build out their own facilities. The expense is relative to how much expertise you have in construction of scientific apparatus, most of the costs are labor. If you can build out your own facility and equipment its not as expensive as you might think and for 99.5% of applications it does not have to be as clean as you think it does. A group of researchers can throw up a temp controled concrete floor sealed with a metal building and then build out the equipment in solid works and find a good machinist or pick up a VMC on a bid site or govt liquidation. Elon Musk proved this and he upset the apple cart in doing so. Groveling for grants just to burn it up on rent to produce some paper no one will read is not my idea of productive, your on a tight time line with a grant and you get what you get out of the clean room work. You would need ALOT of lab time to actually produce any intellectual property and if you are tied into the university and govt grants you might get a few bucks on a break through or worse you just wasted a bunch of your time and the govts money and your still driving a jalopy.
  10. Apr 13, 2017 #9
    I agree with everything you just said, and I really, really like the way you put that. Thanks for the advice.
  11. Apr 13, 2017 #10


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    What's a single layer ASIC? Metal-1?

    Even test ICs have multiple layers... :smile:
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