How to Design a J-K Flip Flop Using VHDL?

[hajer jamal]

j_k flip flop .by using vhdl ..please help

hi every body

i hope every things gana be okay

i really have pro,,in my class

so anyone can help me please give is hand to help

any ways ,, my problem is about ,, my doctor give us homework about some things we don't know how to do , so it's about how can design j
j-k flip flop by using vhdl

anyways ,, tnaks a lot

 

[MustangGT]

try this:

Entity T_FF IS
PORT( T, Clock : IN STD_LOGIC;
Q : OUT STD_LOGIC;
END T_FF;
ARCHITECTURE Behavior OF T_FF IS
signal tmp : STD_LOGIC;
BEGIN
PROCESS (Clock)
BEGIN
IF Clock' EVENT AND Clock = '1' THEN
if T = '1' THEN
tmp <= NOT tmp;
else
tmp <= tmp;
end IF;
END IF;
END PROCESS;
Q <= tmp;
END Behavior

 

[hajer jamal]

thanks a lot for help
and i still search for good one