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Sketching the Moore state diagram of a sequential circuit with J-K Flip Flops

  1. Aug 20, 2012 #1
    1. The problem statement, all variables and given/known data
    Sketch the moore state diagram for the circuit shown in the figure, where A is the input variable. You may assume initially that Q[2:0] = 000.

    CLK = clock.

    The box with the & inside is an AND gate.

    Q[2:0] means that initially Q0, Q1, and Q2 = 0 and hence there inverses are equal to one.

    2. Relevant equations

    None.

    3. The attempt at a solution

    I understand the layout of the Moore diagram, a bubble for each state, with a slash and the corresponding output next to it.

    XX / XX

    STATE NUMBER
    OUTPUT OF THAT STATE

    Furthermore, an arrow is used to represent all possible transitions between states and the labels on the arrows show the required conditions for the transit.

    What I am having issues with is actually drawing the diagram. Supposing A = 0, when the first clock pulse arrives, Q2 will still be 0. This will happen continuously as long as A = 0.

    The difficulty arrives when we set A=1, then as far as I can see the output of Q2 will STILL be 0 ? Do I represent this as an intermediary state, with output still 0 as was the output of Q2 was in state 1, or just draw an arrow from state 1 to itself ?

    Supposing the next A=1 is input at the clock pulse, will the output of Q2 STILL not be 0? (as the one hasn't travlled through the circuit yet). Once again, intermediary state ? I believe that at the next A = 1 clock pulse the output of Q2 will be 1.

    Supposing another A = 1 (this time K=1 too), the output of Q2 will now be 0 again.

    I haven't even considered instances where a 1 is followed be a 0, or 2 1's are followed be a 0. I feel like I am thoroughly overcomplicating this problem and any guidance will be very much appreciated !

    I have attached the question and my partial solution.
    1. The problem statement, all variables and given/known data



    2. Relevant equations



    3. The attempt at a solution
    1. The problem statement, all variables and given/known data



    2. Relevant equations



    3. The attempt at a solution
     

    Attached Files:

  2. jcsd
  3. Aug 20, 2012 #2
    My working solution :)
     

    Attached Files:

  4. Aug 20, 2012 #3

    berkeman

    User Avatar

    Staff: Mentor

    Welcome to the PF.

    You have 3 FFs, so how many possible states are there?

    And when you are in a particular state, the input A can be either a 1 or a 0 to affect the transition to the next state at the next clock rising edge.

    So I would start with a truth table with all the states listed, and then list what the next state will be for both the case of A=0 and A=1. Once you have the table, you can draw the diagram.

    Note that all the states in the table may not be reachable starting with the outputs = 000. In real circuit design, we make sure that these "illegal" states have a transision back to the reset state (in this case 000), to be sure the circuit does not hang if there is a disturbance (like an ESD hit) that temporarily scrambles the circuit.
     
  5. Aug 21, 2012 #4
    Okay, I see what you mean. So with 3 flip flops I have the following states,

    000, 001, 010, 011, 100, 101, 110, 111.

    So what you're saying is that these states should be the contents of my bubbles and then I need to consider what state they would transition to if A = 1 or A = 0, and draw my arrows accordingly.

    I'll give that a go. Many thanks and much appreciated !!
     
  6. Aug 21, 2012 #5
    Ok, I have considered the A= 0 and A= 1 case for each and every state and here are my results. If you could verify them, as well as checking my diagrams and telling me if I could omit certain states (as they cannot be obtained from 000), then I would be extremely grateful !

    Thanks for your time,

    Biren
     

    Attached Files:

  7. Aug 21, 2012 #6

    berkeman

    User Avatar

    Staff: Mentor

    Looks like good work. I didn't check the state transitions in detail, but a few comments:

    ** Note how in the original problem statement, even though the FF outputs are numbered left to right as Q0, Q1, Q2, the ordered triple Q[2:0] has the FF outputs listed right to left. that is generally the convention in logic design, so you should re-number your HDL listing (the left page) and the state diagram accordingly.

    ** Also, it is the convention to call the first state "0" and go up from there. So instead of numbering the states 1-8, you should probably renumber them 0-7.

    ** In the full diagram in the middle, you can move the final "illegal" state (now to be renumbered as state 7) over to the left to put it adjacent to the 000 state. Does it actually naturally go to the 000 state? (I'll check that when I have time)

    ** I'm not sure what you mean by your 2nd state diagram, only showing some of the states. The circuit with 3FFs is capable of all 8 states, so I'm thinking you should show them all. Did I miss something?

    :smile:
     
  8. Aug 21, 2012 #7

    berkeman

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    Staff: Mentor

    Yes, it looks like it does.
     
  9. Aug 22, 2012 #8
    Thanks so much ! I really appreciate it.

    With regards to the second state diagram, I was thinking that certain states cannot be obtained by starting from 000 (bar some external factor), and therefore wondered if leaving those states out (perhaps with an explanation) would be ok ? Of course, this shouldn't make any difference as long as my solution has the full state diagram too !
     
  10. Aug 22, 2012 #9

    berkeman

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    Staff: Mentor

    Yes, definitely show the full diagram first. You could even highlight the "illegal" states, and mention that they are shown to ensure that there is a path back to the "normal" states from them. That is what we have to do in the real world, or else you can end up with a chip that can lock up and not recover after a transient event.

    You could optionally then show a simplified diagram of just the regular states that the machine goes through in normal operation. Or alternately, you could draw the full diagram with a box around the normal states, and the "illegal" states outside that box, with their transitions shown going to the states inside the box.
     
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